Simulation Results: lc_ctrl/volatile_unlock_disabled

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.25 %
  • code
  • 91.55 %
  • assert
  • 95.97 %
  • func
  • 83.23 %
  • block
  • 96.52 %
  • line
  • 97.23 %
  • branch
  • 91.15 %
  • toggle
  • 82.58 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 61.496us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 64.211us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.866us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 141.536us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 19.702us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 21.228us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 14.866us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 19.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 59.493us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 2227.746us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 12.393us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 68.734us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.000s 1392.231us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_ctrl_prog_failure 3.000s 68.734us 1 1 100.00
lc_ctrl_errors 8.000s 1392.231us 1 1 100.00
lc_ctrl_security_escalation 6.000s 379.051us 1 1 100.00
lc_ctrl_jtag_state_failure 5.000s 404.735us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.000s 121.012us 0 1 0.00
lc_ctrl_jtag_errors 23.000s 9129.911us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 6.000s 437.262us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 2396.104us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 121.012us 0 1 0.00
lc_ctrl_jtag_errors 23.000s 9129.911us 1 1 100.00
lc_ctrl_jtag_access 4.000s 368.974us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.000s 2072.782us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 769.773us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 289.899us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 1601.111us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 79.712us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 32.655us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 227.063us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 45.148us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.000s 1082.431us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 48.678us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 27.000s 4251.897us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 22.336us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 124.877us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 124.877us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 64.211us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.866us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 19.702us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 31.606us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 64.211us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.866us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 19.702us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 31.606us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 129.445us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 323.023us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 323.023us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 2227.746us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.445us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.445us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.445us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.445us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.445us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.445us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.445us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 209.902us 1 1 100.00
lc_ctrl_sec_cm 3.000s 129.445us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 379.051us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 59.493us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 2396.104us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 203.427us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 203.427us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 1744.115us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 417.962us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 417.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 2.000s 109.492us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 38807696378708149521542183870065218341145557365719444243182675671402258585681 259
UVM_INFO @ 404734566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 27491186542699801182489182633727724429263535422358571355029654548180912529385 2109
UVM_INFO @ 4251896559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 60939296425542537312157054471469957483321174260276727090684309530734710303789 195
UVM_INFO @ 121011682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 10919650687425832376705589832819230126278490112828609884498160051079931138 179
UVM_INFO @ 109491534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---