Simulation Results: lc_ctrl/volatile_unlock_enabled

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.78 %
  • code
  • 93.28 %
  • assert
  • 96.25 %
  • func
  • 85.81 %
  • block
  • 97.02 %
  • line
  • 97.63 %
  • branch
  • 92.45 %
  • toggle
  • 85.43 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.000s 625.286us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 23.192us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 27.877us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 427.309us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 123.034us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 37.385us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 27.877us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 123.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 52.887us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 415.537us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 59.061us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 472.374us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 1405.050us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_ctrl_prog_failure 3.000s 472.374us 1 1 100.00
lc_ctrl_errors 5.000s 1405.050us 1 1 100.00
lc_ctrl_security_escalation 6.000s 1254.019us 1 1 100.00
lc_ctrl_jtag_state_failure 2.000s 110.600us 0 1 0.00
lc_ctrl_jtag_prog_failure 5.000s 244.368us 0 1 0.00
lc_ctrl_jtag_errors 21.000s 15806.778us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 5.000s 335.723us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1347.222us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 244.368us 0 1 0.00
lc_ctrl_jtag_errors 21.000s 15806.778us 1 1 100.00
lc_ctrl_jtag_access 6.000s 427.900us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.000s 19199.396us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 321.516us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 153.172us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 1799.600us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 1302.087us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 38.327us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 128.905us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 47.963us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 12.000s 3415.004us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 45.344us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 70.000s 6725.803us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 15.613us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 132.673us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 132.673us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 23.192us 1 1 100.00
lc_ctrl_csr_rw 1.000s 27.877us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 123.034us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 194.904us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 23.192us 1 1 100.00
lc_ctrl_csr_rw 1.000s 27.877us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 123.034us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 194.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 871.029us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 131.676us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 131.676us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 415.537us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_ctrl_sec_cm 4.000s 871.029us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_ctrl_sec_cm 4.000s 871.029us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_ctrl_sec_cm 4.000s 871.029us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_ctrl_sec_cm 4.000s 871.029us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_ctrl_sec_cm 4.000s 871.029us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_ctrl_sec_cm 4.000s 871.029us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_ctrl_sec_cm 4.000s 871.029us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 500.268us 1 1 100.00
lc_ctrl_sec_cm 4.000s 871.029us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1254.019us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 52.887us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1347.222us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.000s 2211.163us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.000s 2211.163us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 473.369us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 1400.388us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 1400.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 24.000s 1785.011us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 44650750900282143070624861170449849908498896623632903451969749736448433498586 178
UVM_INFO @ 110599583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 92765648049215607145211453814525295543814472021766540418193400079287623825991 4206
UVM_INFO @ 6725802675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 20420607050522795630612189837042020714003569600440833437720070148238172880836 330
UVM_INFO @ 244367758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 66058894376517838877428775306586553188287202919905831752471689531511879279344 1507
UVM_INFO @ 1785011270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---