Simulation Results: otp_ctrl

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.65 %
  • code
  • 70.53 %
  • assert
  • 91.53 %
  • func
  • 49.88 %
  • line
  • 87.08 %
  • branch
  • 82.31 %
  • cond
  • 85.02 %
  • toggle
  • 62.50 %
  • FSM
  • 35.72 %
Validation stages
V1
77.78%
V2
60.00%
V2S
44.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.650s 828.228us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 3.850s 132.069us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.090s 113.033us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.440s 73.932us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 12.130s 9311.272us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.160s 98.650us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.890s 30.098us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.440s 73.932us 1 1 100.00
otp_ctrl_csr_aliasing 3.160s 98.650us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.270s 629.541us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.840s 50.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 154.390s 11145.205us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 5.870s 758.046us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 10.130s 905.797us 0 1 0.00
otp_ctrl_check_fail 3.180s 245.486us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 3.900s 901.859us 0 1 0.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 9.760s 4407.632us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 5.370s 636.974us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 12.870s 706.829us 1 1 100.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 12.160s 483.608us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 15.560s 838.192us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 27.330s 1648.827us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 185.910s 63379.644us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.610s 613.866us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.000s 209.176us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 8.340s 462.472us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 8.340s 462.472us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.090s 113.033us 1 1 100.00
otp_ctrl_csr_rw 2.440s 73.932us 1 1 100.00
otp_ctrl_csr_aliasing 3.160s 98.650us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.470s 1486.627us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.090s 113.033us 1 1 100.00
otp_ctrl_csr_rw 2.440s 73.932us 1 1 100.00
otp_ctrl_csr_aliasing 3.160s 98.650us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.470s 1486.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
otp_ctrl_tl_intg_err 36.580s 1422.714us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 36.580s 1422.714us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 3.850s 132.069us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 3.850s 132.069us 0 1 0.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_dai_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
otp_ctrl_macro_errs 15.560s 838.192us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
sec_cm_timer_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_dai_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
otp_ctrl_macro_errs 15.560s 838.192us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
sec_cm_timer_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 5.770s 896.965us 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 5.870s 758.046us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.180s 245.486us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 9.760s 4407.632us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 9.760s 4407.632us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 9.760s 4407.632us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 9.760s 4407.632us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 9.760s 4407.632us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 3.850s 132.069us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 9.760s 4407.632us 1 1 100.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 3.850s 132.069us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 229.000s 17036.420us 0 1 0.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 3.900s 901.859us 0 1 0.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 3.850s 132.069us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 3.850s 132.069us 0 1 0.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 15.560s 838.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 91.300s 62516.643us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 60.270s 5207.203us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 3 test runs
otp_ctrl_smoke 56572344653300133724308942065528258218827751036371976037850603012592872228127 2250
UVM_INFO @ 132068799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_partition_walk 104568654050956648586692415138353533965082267747302969349603411513985110437680 160061
UVM_INFO @ 11145205055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 28166627734676998094427835640018036366827369983178977786963549905297038877735 1358
UVM_INFO @ 901859309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_background_chks 39063836922477126218970124733537530893526944560970022866410163765928827785291 3894
UVM_INFO @ 905796538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 89676850580124995860154025997980904634249475560214018630885103560167146280973 2304
UVM_INFO @ 636973849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59823080409792831511414933802138624522199377153312777465599063173230797754981 8328
UVM_INFO @ 5207203188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 2 test runs
otp_ctrl_low_freq_read 110011045688520355311889609156102561559337802530321822239854389042658105732239 95
UVM_INFO @ 62516643268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 70277235583816420475257148687340403148866567146488522722140650326319632719806 5834
UVM_INFO @ 63379644178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:474) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
otp_ctrl_parallel_lc_esc 68760450940496535730679295678177367784912830549768088678081543464538341295865 455
UVM_INFO @ 896964789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 78080804630440042263682830123041169696572736645868337092890527702462412124726 724
UVM_INFO @ 245486314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_test_access 114993440672324515276624375424854456009107448844878914290886542129176915851462 11418
UVM_INFO @ 1648827359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_bus_integ_error) did not fire in * cycles. 1 test run
otp_ctrl_sec_cm 26634508669890416096882367492388206146954542531493077872640646634342455833850 1717
UVM_INFO @ 17036419549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2202) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 98751524553525370073784127014616048407158523488883030001902676562537562643455 97
UVM_INFO @ 30097799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---