Simulation Results: rom_ctrl/32kb

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.60 %
  • code
  • 82.92 %
  • assert
  • 96.80 %
  • func
  • 89.07 %
  • block
  • 87.72 %
  • line
  • 89.69 %
  • branch
  • 81.16 %
  • toggle
  • 84.65 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 226.256us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 68.847us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 63.854us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 107.188us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 57.542us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 124.331us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 63.854us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 57.542us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 72.037us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 79.246us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 796.435us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.000s 765.448us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 62.026us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 52.385us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 533.857us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 533.857us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 68.847us 1 1 100.00
rom_ctrl_csr_rw 3.000s 63.854us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 57.542us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 92.524us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 68.847us 1 1 100.00
rom_ctrl_csr_rw 3.000s 63.854us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 57.542us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 92.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 759.954us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 71.000s 1344.576us 1 1 100.00
rom_ctrl_tl_intg_err 25.000s 204.096us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 71.000s 1344.576us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 71.000s 1344.576us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 71.000s 1344.576us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 71.000s 1344.576us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 226.256us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 226.256us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 226.256us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 25.000s 204.096us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 62.026us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 26.000s 3773.194us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 759.954us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 71.000s 1344.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 17.000s 8622.093us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 5730969954818129155718883902013992708771338237443003353849365033594794155191 88
UVM_INFO @ 796435310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:480) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 107267859662516506488578234457027167807255004827501236728314095872783714861796 103
UVM_INFO @ 8622093292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---