Simulation Results: rom_ctrl/64kb

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.98 %
  • code
  • 82.73 %
  • assert
  • 97.23 %
  • func
  • 95.96 %
  • block
  • 87.14 %
  • line
  • 88.61 %
  • branch
  • 81.40 %
  • toggle
  • 84.74 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 409.572us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.000s 97.289us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.000s 57.960us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 70.625us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 125.661us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 115.429us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.000s 57.960us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 125.661us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 73.458us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 59.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 2.220us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.000s 433.481us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 65.223us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 86.881us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 547.526us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 547.526us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 97.289us 1 1 100.00
rom_ctrl_csr_rw 4.000s 57.960us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 125.661us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 62.806us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 97.289us 1 1 100.00
rom_ctrl_csr_rw 4.000s 57.960us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 125.661us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 62.806us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 164.072us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 272.000s 840.926us 1 1 100.00
rom_ctrl_tl_intg_err 58.000s 444.044us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 272.000s 840.926us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 272.000s 840.926us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 272.000s 840.926us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 272.000s 840.926us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 409.572us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 409.572us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 409.572us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 58.000s 444.044us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 65.223us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 66.000s 57814.632us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 164.072us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 272.000s 840.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 10.000s 730.208us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 34536834270190661166618062901814848017551724052854454453148843862483814166817 88
UVM_INFO @ 2219712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:480) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 19575718506693224486984790788771222955424373277336842125610913581118490189859 92
UVM_INFO @ 730208066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---