Simulation Results: rstmgr

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.57 %
  • code
  • 99.30 %
  • assert
  • 98.53 %
  • func
  • 97.89 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.75 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.890s 69.898us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.470s 63.292us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.190s 37.293us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.370s 81.874us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.390s 39.123us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.060s 94.494us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.190s 37.293us 1 1 100.00
rstmgr_csr_aliasing 1.390s 39.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.760s 131.354us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.630s 47.415us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.490s 65.788us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 8.170s 661.906us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 8.170s 661.906us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 8.170s 661.906us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 8.170s 661.906us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 15.910s 2364.668us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.110s 38.821us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.950s 46.128us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.950s 46.128us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.470s 63.292us 1 1 100.00
rstmgr_csr_rw 1.190s 37.293us 1 1 100.00
rstmgr_csr_aliasing 1.390s 39.123us 1 1 100.00
rstmgr_same_csr_outstanding 1.410s 37.340us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.470s 63.292us 1 1 100.00
rstmgr_csr_rw 1.190s 37.293us 1 1 100.00
rstmgr_csr_aliasing 1.390s 39.123us 1 1 100.00
rstmgr_same_csr_outstanding 1.410s 37.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 21.230s 3398.493us 1 1 100.00
rstmgr_tl_intg_err 7.130s 623.634us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 21.230s 3398.493us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 21.230s 3398.493us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 7.130s 623.634us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.650s 62.241us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.250s 482.922us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.500s 291.691us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 21.230s 3398.493us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.190s 37.293us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.190s 37.293us 1 1 100.00