Simulation Results: rv_timer

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 96.04 %
  • code
  • 90.45 %
  • assert
  • 98.10 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 701.490us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 40.688us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 85.579us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 4.000s 345.460us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 14.324us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 21.285us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 85.579us 1 1 100.00
rv_timer_csr_aliasing 1.000s 14.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 234.259us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 2226.038us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 451.000s 1891366.062us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 451.000s 1891366.062us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 13.000s 2706.272us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 42.068us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 71.230us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 1508.510us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 1508.510us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 40.688us 1 1 100.00
rv_timer_csr_rw 1.000s 85.579us 1 1 100.00
rv_timer_csr_aliasing 1.000s 14.324us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 43.964us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 40.688us 1 1 100.00
rv_timer_csr_rw 1.000s 85.579us 1 1 100.00
rv_timer_csr_aliasing 1.000s 14.324us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 43.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 37.557us 1 1 100.00
rv_timer_tl_intg_err 2.000s 106.813us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 106.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 584.856us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 46.312us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 23.000s 3052.781us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 53436680738450419645162721249467806171037174908746264140992332207585354070048 84
UVM_INFO @ 584856387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 75869447727687789126426916037367348337080635423766096998157482074468491334128 84
UVM_INFO @ 46312268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---