Simulation Results: spi_host

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.50 %
  • code
  • 91.30 %
  • assert
  • 94.14 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 52.000s 2227.003us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 23.746us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 18.158us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 197.115us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 32.423us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 28.224us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 18.158us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.423us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 38.670us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 34.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 23.895us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 33.925us 1 1 100.00
spi_host_error_cmd 1.000s 21.311us 1 1 100.00
spi_host_event 7.000s 665.414us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 149.526us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 149.526us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 149.526us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 347.000s 45266.430us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 109.611us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 91.872us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 149.526us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 149.526us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 52.000s 2227.003us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 52.000s 2227.003us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 86.050us 1 1 100.00
spien 1 1 100.00
spi_host_spien 7.000s 2281.418us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 23.000s 3788.656us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 91.008us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 33.925us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 35.868us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 21.689us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 289.769us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 289.769us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 23.746us 1 1 100.00
spi_host_csr_rw 1.000s 18.158us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.423us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 32.348us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 23.746us 1 1 100.00
spi_host_csr_rw 1.000s 18.158us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.423us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 32.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 308.143us 1 1 100.00
spi_host_sec_cm 2.000s 120.759us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 308.143us 1 1 100.00