Simulation Results: sram_ctrl/main

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.60 %
  • code
  • 94.98 %
  • assert
  • 97.83 %
  • func
  • 94.00 %
  • block
  • 95.15 %
  • line
  • 95.71 %
  • branch
  • 92.37 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.000s 691.889us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 23.271us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.283us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 130.116us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.985us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 378.218us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 24.283us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.985us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 169.000s 16375.241us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 77.000s 9987.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 14.000s 3444.113us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 213.000s 8827.035us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 180.000s 7487.057us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 20.000s 6674.675us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 43.000s 11162.464us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 11.000s 1618.288us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 685.021us 1 1 100.00
sram_ctrl_partial_access_b2b 358.000s 244150.218us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 7.000s 3708.425us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 2776.027us 1 1 100.00
sram_ctrl_throughput_w_readback 6.000s 3044.575us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 507.259us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1208.944us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 7.000s 691.889us 1 1 100.00
sram_ctrl_partial_access 5.000s 685.021us 1 1 100.00
sram_ctrl_access_during_key_req 20.000s 6674.675us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 246.000s 47771.647us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 35.596us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 133.498us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 133.498us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 23.271us 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.283us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.985us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 26.719us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 23.271us 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.283us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.985us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 26.719us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 38.000s 28234.719us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 347.179us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 180.292us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 347.179us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 180.292us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 507.259us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 507.259us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.283us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 11.000s 1618.288us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 1618.288us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 1618.288us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 43.000s 11162.464us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 6.000s 9727.668us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 38.000s 28234.719us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2826.290us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 691.889us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 691.889us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 11.000s 1618.288us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 347.179us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 43.000s 11162.464us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 347.179us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 347.179us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.000s 691.889us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 347.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 71.000s 11571.256us 1 1 100.00