Simulation Results: sram_ctrl/ret

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.98 %
  • code
  • 82.38 %
  • assert
  • 97.81 %
  • func
  • 92.76 %
  • block
  • 93.82 %
  • line
  • 94.91 %
  • branch
  • 89.64 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 248.064us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 19.341us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.455us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 62.409us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.440us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 62.816us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 12.455us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.440us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 12.000s 857.979us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 8.000s 101.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 15.000s 477.334us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 184.000s 27646.147us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 11.000s 9729.161us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 31.000s 1288.179us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 8.000s 2110.216us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 18.000s 1099.629us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 80.713us 1 1 100.00
sram_ctrl_partial_access_b2b 276.000s 5481.288us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 7.000s 208.422us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 38.573us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 145.629us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 20.000s 6273.370us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 31.000us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 248.064us 1 1 100.00
sram_ctrl_partial_access 2.000s 80.713us 1 1 100.00
sram_ctrl_access_during_key_req 31.000s 1288.179us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 73.000s 6008.806us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 49.045us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 142.015us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 142.015us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 19.341us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.455us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.440us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 34.648us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 19.341us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.455us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.440us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 34.648us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 377.837us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 772.293us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 406.763us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 772.293us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 406.763us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 20.000s 6273.370us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 20.000s 6273.370us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.455us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 18.000s 1099.629us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 18.000s 1099.629us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 18.000s 1099.629us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 8.000s 2110.216us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 133.868us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 377.837us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 242.095us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 248.064us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 248.064us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 18.000s 1099.629us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 772.293us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 8.000s 2110.216us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 772.293us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 772.293us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 248.064us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 772.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 35.000s 2514.042us 1 1 100.00