TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Tuesday November 11 2025 17:32:35 UTC

GitHub Revision: b700cc2

Branch: master

Name	Passing	Total	Pass Rate	Coverage
TL_AGENT	1418	1546	91.72	--
ADC_CTRL	1418	1546	91.72	90.36
AES/UNMASKED	1418	1546	91.72	92.29
AES/MASKED	1418	1546	91.72	95.18
AON_TIMER	1418	1546	91.72	97.43
CSRNG	1418	1546	91.72	94.61
EDN	1418	1546	91.72	83.41
ENTROPY_SRC/RNG_4BITS	1418	1546	91.72	88.40
HMAC	1418	1546	91.72	90.14
I2C	1418	1546	91.72	83.33
KEYMGR	1418	1546	91.72	90.43
KMAC/MASKED	1418	1546	91.72	92.32
KMAC/UNMASKED	1418	1546	91.72	90.61
LC_CTRL/VOLATILE_UNLOCK_DISABLED	1418	1546	91.72	85.54
LC_CTRL/VOLATILE_UNLOCK_ENABLED	1418	1546	91.72	85.75
OTBN	1418	1546	91.72	93.40
PATTGEN	1418	1546	91.72	98.42
PRIM_ALERT	1418	1546	91.72	94.25
PRIM_ESC	1418	1546	91.72	83.94
PRIM_LFSR	1418	1546	91.72	98.31
PRIM_PRESENT	1418	1546	91.72	93.41
PRIM_PRINCE	1418	1546	91.72	100.00
ROM_CTRL/32KB	1418	1546	91.72	97.12
ROM_CTRL/64KB	1418	1546	91.72	96.42
RV_DM/USE_JTAG_INTERFACE	1418	1546	91.72	78.35
RV_TIMER	1418	1546	91.72	98.68
SPI_HOST	1418	1546	91.72	95.84
SPI_DEVICE/1R1W	1418	1546	91.72	88.81
SPI_DEVICE/2P	1418	1546	91.72	90.69
SRAM_CTRL/MAIN	1418	1546	91.72	94.07
SRAM_CTRL/RET	1418	1546	91.72	91.11
SYSRST_CTRL	1418	1546	91.72	89.28
UART	1418	1546	91.72	89.71
USBDEV	1418	1546	91.72	91.73
GPIO	1418	1546	91.72	98.12
ALERT_HANDLER	1418	1546	91.72	93.22
CLKMGR	1418	1546	91.72	96.77
FLASH_CTRL	1418	1546	91.72	94.66
OTP_CTRL	1418	1546	91.72	79.73
PWM	1418	1546	91.72	98.25
PWRMGR	1418	1546	91.72	95.09
RSTMGR_CNSTY_CHK	1418	1546	91.72	95.87
RSTMGR	1418	1546	91.72	98.39
XBAR_MAIN	1418	1546	91.72	96.43
XBAR_PERI	1418	1546	91.72	85.34
CHIP	1418	1546	91.72	79.93