Simulation Results: adc_ctrl

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.98 %
  • code
  • 95.93 %
  • assert
  • 95.62 %
  • func
  • 36.40 %
  • line
  • 99.02 %
  • branch
  • 98.51 %
  • cond
  • 95.62 %
  • toggle
  • 100.00 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.610s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.260s 0.000us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.990s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 13.390s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.360s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.710s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.990s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 2.360s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 269.550s 0.000us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 519.190s 0.000us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 110.050s 0.000us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 78.160s 0.000us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 199.890s 0.000us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 111.280s 0.000us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 273.780s 0.000us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 544.430s 0.000us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.360s 0.000us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 6.120s 0.000us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 126.920s 0.000us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 265.600s 0.000us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.860s 0.000us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.060s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 3.020s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 3.020s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.260s 0.000us 1 1 100.00
adc_ctrl_csr_rw 0.990s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 2.360s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 12.410s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.260s 0.000us 1 1 100.00
adc_ctrl_csr_rw 0.990s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 2.360s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 12.410s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 8.150s 0.000us 1 1 100.00
adc_ctrl_tl_intg_err 16.740s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 16.740s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 11.820s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 26023612395350228806017981778906432243980176790801257100062663454473634240192 338
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---