Simulation Results: chip

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.52 %
  • code
  • 85.06 %
  • assert
  • 97.25 %
  • func
  • 44.26 %
  • line
  • 94.29 %
  • branch
  • 93.49 %
  • cond
  • 89.21 %
  • toggle
  • 91.19 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
84.56%
V2S
50.00%
V3
63.33%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 135.360s 0.000us 1 1 100.00
chip_sw_example_rom 59.400s 0.000us 1 1 100.00
chip_sw_example_manufacturer 121.800s 0.000us 1 1 100.00
chip_sw_example_concurrency 141.180s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 233.240s 0.000us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 358.750s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 2651.100s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5428.220s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 304.400s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5428.220s 0.000us 1 1 100.00
chip_csr_rw 358.750s 0.000us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.100s 0.000us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 267.970s 0.000us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 267.970s 0.000us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 267.970s 0.000us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 353.600s 0.000us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 353.600s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx1 326.530s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx2 411.350s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx3 369.020s 0.000us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 907.340s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 951.420s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 639.750s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 121.300s 0.000us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 121.300s 0.000us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 223.620s 0.000us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 340.650s 0.000us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 154.510s 0.000us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 565.310s 0.000us 1 1 100.00
chip_tap_straps_testunlock0 97.820s 0.000us 1 1 100.00
chip_tap_straps_rma 316.090s 0.000us 1 1 100.00
chip_tap_straps_prod 88.230s 0.000us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 195.540s 0.000us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 772.780s 0.000us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 447.930s 0.000us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 447.930s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 670.210s 0.000us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1001.150s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 363.500s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 535.260s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3530.950s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 190.380s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 565.340s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 213.020s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 990.030s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 166.970s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 382.860s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 119.770s 0.000us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 183.330s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 490.060s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 211.170s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 175.950s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 211.170s 0.000us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 164.500s 0.000us 1 1 100.00
chip_sw_aes_smoketest 191.190s 0.000us 1 1 100.00
chip_sw_aon_timer_smoketest 163.830s 0.000us 1 1 100.00
chip_sw_clkmgr_smoketest 126.470s 0.000us 1 1 100.00
chip_sw_csrng_smoketest 174.030s 0.000us 1 1 100.00
chip_sw_entropy_src_smoketest 755.100s 0.000us 1 1 100.00
chip_sw_gpio_smoketest 187.030s 0.000us 1 1 100.00
chip_sw_hmac_smoketest 194.520s 0.000us 1 1 100.00
chip_sw_kmac_smoketest 164.580s 0.000us 1 1 100.00
chip_sw_otbn_smoketest 1296.170s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 317.450s 0.000us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 272.070s 0.000us 1 1 100.00
chip_sw_rv_plic_smoketest 160.800s 0.000us 1 1 100.00
chip_sw_rv_timer_smoketest 144.110s 0.000us 1 1 100.00
chip_sw_rstmgr_smoketest 189.090s 0.000us 1 1 100.00
chip_sw_sram_ctrl_smoketest 169.500s 0.000us 1 1 100.00
chip_sw_uart_smoketest 135.710s 0.000us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 182.540s 0.000us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 370.710s 0.000us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7396.450s 0.000us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2495.470s 0.000us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 141.230s 0.000us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 190.970s 0.000us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 154.030s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6898.180s 0.000us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7130.100s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 50.510s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 50.510s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5428.220s 0.000us 1 1 100.00
chip_same_csr_outstanding 1296.700s 0.000us 1 1 100.00
chip_csr_hw_reset 233.240s 0.000us 1 1 100.00
chip_csr_rw 358.750s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5428.220s 0.000us 1 1 100.00
chip_same_csr_outstanding 1296.700s 0.000us 1 1 100.00
chip_csr_hw_reset 233.240s 0.000us 1 1 100.00
chip_csr_rw 358.750s 0.000us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 26.310s 0.000us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.940s 0.000us 1 1 100.00
xbar_smoke_large_delays 52.740s 0.000us 1 1 100.00
xbar_smoke_slow_rsp 42.540s 0.000us 1 1 100.00
xbar_random_zero_delays 7.660s 0.000us 1 1 100.00
xbar_random_large_delays 24.510s 0.000us 1 1 100.00
xbar_random_slow_rsp 221.580s 0.000us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 21.690s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 15.480s 0.000us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 13.070s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 15.480s 0.000us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 87.880s 0.000us 1 1 100.00
xbar_access_same_device_slow_rsp 306.760s 0.000us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 45.570s 0.000us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 153.640s 0.000us 1 1 100.00
xbar_stress_all_with_error 122.790s 0.000us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 339.160s 0.000us 1 1 100.00
xbar_stress_all_with_reset_error 60.620s 0.000us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2495.470s 0.000us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2385.240s 0.000us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2467.910s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2089.360s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2547.140s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2551.230s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2645.490s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2600.690s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 17.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 18.340s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 17.050s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 18.370s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 26.690s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 23.790s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 18.080s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 17.370s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 16.650s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.210s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.340s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.120s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.610s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 18.440s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 17.300s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.580s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 17.010s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.310s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.770s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 18.400s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.560s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 17.400s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18.060s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.120s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.030s 0.000us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1929.200s 0.000us 1 1 100.00
rom_e2e_asm_init_dev 2544.560s 0.000us 1 1 100.00
rom_e2e_asm_init_prod 2387.230s 0.000us 1 1 100.00
rom_e2e_asm_init_prod_end 2435.180s 0.000us 1 1 100.00
rom_e2e_asm_init_rma 2463.160s 0.000us 1 1 100.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 2267.930s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 4294.560s 0.000us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2317.620s 0.000us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2489.410s 0.000us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3215.080s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3215.080s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 173.270s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 190.380s 0.000us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 185.600s 0.000us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 177.020s 0.000us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1878.670s 0.000us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 208.940s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 329.620s 0.000us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 423.290s 0.000us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 575.700s 0.000us 1 1 100.00
chip_plic_all_irqs_10 307.390s 0.000us 1 1 100.00
chip_plic_all_irqs_20 388.890s 0.000us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 177.460s 0.000us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1100.720s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 323.560s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 124.540s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 618.630s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1344.120s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 761.210s 0.000us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7056.380s 0.000us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 268.280s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 317.450s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 268.280s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 456.800s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 456.800s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 218.670s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 422.350s 0.000us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 572.540s 0.000us 1 1 100.00
chip_sw_aes_idle 177.020s 0.000us 1 1 100.00
chip_sw_hmac_enc_idle 192.790s 0.000us 1 1 100.00
chip_sw_kmac_idle 159.700s 0.000us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 245.780s 0.000us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 292.260s 0.000us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 295.840s 0.000us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 238.370s 0.000us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 767.080s 0.000us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 356.460s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 342.480s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 378.630s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 377.420s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 372.990s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 376.290s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 670.210s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 725.400s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 378.630s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 377.420s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 363.500s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 535.260s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3530.950s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 190.380s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 565.340s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 213.020s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 990.030s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 166.970s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 382.860s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 119.770s 0.000us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 151.010s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 404.690s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 609.760s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 2983.100s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 163.960s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 152.260s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1224.050s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 196.670s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 360.790s 0.000us 1 1 100.00
chip_sw_flash_init_reduced_freq 1020.820s 0.000us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 9565.320s 0.000us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 670.210s 0.000us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 388.760s 0.000us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 252.910s 0.000us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 423.290s 0.000us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 618.630s 0.000us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 789.470s 0.000us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 179.140s 0.000us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 458.780s 0.000us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 151.740s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2713.930s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 136.450s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 761.700s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 136.450s 0.000us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 789.470s 0.000us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 139.000s 0.000us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1368.960s 0.000us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 549.700s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 535.260s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 319.250s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 363.500s 0.000us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3630.580s 0.000us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1368.960s 0.000us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 226.580s 0.000us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1551.040s 0.000us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 202.110s 0.000us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3630.580s 0.000us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 202.110s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 202.110s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 202.110s 0.000us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 202.110s 0.000us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 423.290s 0.000us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 305.810s 0.000us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 573.290s 0.000us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 443.350s 0.000us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 443.350s 0.000us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 122.870s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 213.020s 0.000us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 192.790s 0.000us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1258.300s 0.000us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 718.150s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 409.930s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 543.320s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 413.240s 0.000us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 316.760s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1551.040s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 990.030s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 663.590s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1878.670s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2031.580s 0.000us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 143.090s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac 197.950s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 166.970s 0.000us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1551.040s 0.000us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 539.950s 0.000us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 165.600s 0.000us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 572.410s 0.000us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 159.700s 0.000us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 329.620s 0.000us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 565.310s 0.000us 1 1 100.00
chip_tap_straps_rma 316.090s 0.000us 1 1 100.00
chip_tap_straps_prod 88.230s 0.000us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 197.030s 0.000us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 539.950s 0.000us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 539.950s 0.000us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 539.950s 0.000us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 964.640s 0.000us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_prim_tl_access 305.810s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 76.920s 0.000us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 202.110s 0.000us 0 1 0.00
chip_sw_flash_rma_unlocked 3630.580s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 175.940s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 423.130s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 588.920s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 565.170s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 539.950s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1551.040s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 362.700s 0.000us 1 1 100.00
chip_sw_sram_ctrl_execution_main 614.160s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 725.400s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 356.460s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 342.480s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 378.630s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 377.420s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 372.990s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 376.290s 0.000us 1 1 100.00
chip_tap_straps_dev 565.310s 0.000us 1 1 100.00
chip_tap_straps_rma 316.090s 0.000us 1 1 100.00
chip_tap_straps_prod 88.230s 0.000us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 153.970s 0.000us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 89.420s 0.000us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 72.020s 0.000us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 138.330s 0.000us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 76.920s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1721.330s 0.000us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 532.470s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 625.990s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 717.810s 0.000us 1 1 100.00
chip_sw_lc_walkthrough_rma 324.500s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1721.330s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 71.400s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 56.240s 0.000us 1 1 100.00
rom_volatile_raw_unlock 63.620s 0.000us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3491.350s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3530.950s 0.000us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 572.540s 0.000us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 572.540s 0.000us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 572.540s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 321.300s 0.000us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 539.950s 0.000us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1368.960s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 321.300s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1551.040s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 373.260s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 132.030s 0.000us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1368.960s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 321.300s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1551.040s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 373.260s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 132.030s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 539.950s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 365.080s 0.000us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 197.030s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 305.810s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 175.940s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 423.130s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 588.920s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 565.170s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 539.950s 0.000us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 305.810s 0.000us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 757.800s 0.000us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 326.580s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1190.130s 0.000us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 277.720s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 408.380s 0.000us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 394.160s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 738.890s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 219.310s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 456.800s 0.000us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 896.510s 0.000us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 383.280s 0.000us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 326.580s 0.000us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 298.780s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2420.970s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 306.220s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 276.000s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 572.970s 0.000us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 664.180s 0.000us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1090.750s 0.000us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1770.670s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 191.460s 0.000us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 423.290s 0.000us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 362.700s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 362.700s 0.000us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1090.750s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 572.970s 0.000us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 383.280s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 317.450s 0.000us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 308.800s 0.000us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 274.430s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 264.360s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1100.720s 0.000us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 197.230s 0.000us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 423.290s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1344.120s 0.000us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 476.490s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 494.950s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 177.390s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 132.030s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 274.430s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 274.430s 0.000us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1528.520s 0.000us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 978.330s 0.000us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 308.800s 0.000us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 234.450s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 332.570s 0.000us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 316.090s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 76.920s 0.000us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 575.700s 0.000us 1 1 100.00
chip_plic_all_irqs_10 307.390s 0.000us 1 1 100.00
chip_plic_all_irqs_20 388.890s 0.000us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 128.020s 0.000us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 170.080s 0.000us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2495.470s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 335.570s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 184.810s 0.000us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 190.850s 0.000us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 179.750s 0.000us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 373.260s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 382.860s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 417.480s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 487.930s 0.000us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 614.160s 0.000us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 423.290s 0.000us 1 1 100.00
chip_sw_data_integrity_escalation 447.930s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 664.180s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1035.900s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 172.550s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 214.250s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 328.620s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1035.900s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1035.900s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2366.200s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2366.200s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 363.640s 0.000us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3215.080s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 166.130s 0.000us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 176.340s 0.000us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 316.340s 0.000us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 301.170s 0.000us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1099.650s 0.000us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5062.920s 0.000us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1764.890s 0.000us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 161.750s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 157.370s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 98.540s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 8909.780s 0.000us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1051.390s 0.000us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 161.000s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 159.700s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 177.180s 0.000us 0 1 0.00
rom_e2e_jtag_inject 1 3 33.33
rom_e2e_jtag_inject_test_unlocked0 72.850s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 201.210s 0.000us 1 1 100.00
rom_e2e_jtag_inject_rma 53.250s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 11.121s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 269.780s 0.000us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 335.510s 0.000us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 747.040s 0.000us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 610.450s 0.000us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 238.990s 0.000us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 598.530s 0.000us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 185.130s 0.000us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 204.910s 0.000us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 358.740s 0.000us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 266.430s 0.000us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1090.750s 0.000us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 161.000s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 159.700s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 177.180s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 427.610s 0.000us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 423.290s 0.000us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5369.910s 0.000us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5369.910s 0.000us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 185.800s 0.000us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 353.600s 0.000us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3174.450s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 215.030s 0.000us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 381.430s 0.000us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.070s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 136.410s 0.000us 1 1 100.00
chip_sw_otp_ctrl_descrambling 170.460s 0.000us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 264.110s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.986s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 198.440s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31614) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 33849160166214892603206425339717711869097720379199634889321737666019534776664 217
UVM_ERROR @ 2261.073542 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31614) { a_addr: 'h10494 a_data: 'h699516bc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h18d20 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2261.073542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 104499182921370703700999018788109763172868641487474435628573720358451991333169 225
UVM_ERROR @ 3410.428268 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10788 read out mismatch
UVM_INFO @ 3410.428268 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 95083630913237184025499748795116785151283403999499132345019396723200795822178 320
UVM_ERROR @ 3319.972760 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3319.972760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 115667283069089953197935718696912064900600632965164335396729044680758672691697 309
UVM_ERROR @ 2802.071040 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 2802.071040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 5326669648541725725953002905175803967370039119116861463834978810484648170492 342
UVM_ERROR @ 7362.637376 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7362.637376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 84922991872044778671066835791408089037038043352197182845226663673811722323868 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3405.612294 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3405.612294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 83969778037017620483106478209173042598081428622483029542430618928139512244517 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3440.511360 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3440.511360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 111870568911692524832387779463502328936011645529112724461660704251148767843761 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 4004242999771943673140702856337670258318214039398114803161917338132530887727 369
UVM_ERROR @ 8484.758885 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8484.758885 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 84009439505656985489746507053594059029581783841392308173720153688860136211914 369
UVM_ERROR @ 8555.951235 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8555.951235 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 57709216216613745773607215222840226429957346481201712499002105002931022518871 341
UVM_ERROR @ 5395.443688 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 5395.443688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@108304) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 110729042199098810998495401635470529348239151432769234236757061294731495891124 333
UVM_ERROR @ 4448.746910 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@108304) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4448.746910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 85968570494600671111394012214274414328115227149268898525561502813798807304470 344
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 13189.119000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13189.119000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 83341501195705881855170778180826490850131748977504618548365200558512280037219 314
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6442.030000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6442.030000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 2726694194127489048752538672214009562557091877272426144193680024038581266300 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 8034.745000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8034.745000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 93829607532935961022410034316694208449764991910926875504135355757378128842213 332
UVM_ERROR @ 34479.815087 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34479.815087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 103493210068387834709891641085517281274801442735983438222466597601615335466361 307
UVM_ERROR @ 2960.984508 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
UVM_INFO @ 2960.984508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 22604727612038696358163503460095825865020965222974090846337682441032930198698 308
UVM_ERROR @ 2353.985064 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2353.985064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 89614471183731959536035640852250543224312973739626951527493935097765759099807 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 17801356711989410267253220591148715058993443296664187256406370390540935879335 343
UVM_ERROR @ 3819.426210 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3819.426210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 21889141354685210414872892113147765694461709156880231002674219884691526175080 None
---- STDERR ----
Another command (pid=1924801) is running. Waiting for it to complete on the server (server_pid=935110)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 59900322059254266390337762003156081229401295812801302338978903157390817785713 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 49811930047238754803039865989776194329478830659692901818997315374301347011558 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 8156050018672976656472269047307258255953164288317161958451882455204896313829 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 93548147182157419765282236961367398240039998570604069982011937143967555555382 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 72364963517970589265049604438353498769372526395700542331565537120032605513792 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 30857251554804753916630789192431737789260749008280117582758013513801590408762 307
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 111545405056103821495220773247742836413481106519410744812925478620201683292050 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 87610193433716866880350731954114259002407170350671565987921421771423734505936 322
UVM_FATAL @ 2952.515448 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2952.515448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 94871247601830328527656246171077042698109927383556757585146450183889595804228 312
UVM_ERROR @ 3168.971000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3168.971000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 1612699298760034326231608853392806289858154032470589787626751749503824664267 318
UVM_ERROR @ 3177.112000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3177.112000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 18806099745492056803965023192246935347259947099373462292295116426281180854183 327
UVM_ERROR @ 10767.641394 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 10767.641394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 91208006812754093651200121550112667842926799611626603640249705433252350477978 349
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 84889029518450609409985176230388785004326390303001911343280133506574228765114 351
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 63954620840415222394846456475642621391639404561460521376865243786160812516959 351
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 115113954005289669950882920663973184389446989006324616389329786696882721229226 351
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 69055814221027134234872376515572881504255524331828824604225145177904588604939 348
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 81284674170498608769231905306213916124060249398549549233822272211934868473519 349
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 59101793147695339237693113636491352732307034617347787786699132653567298598605 347
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 70261114976203395526428973894624890966819544387713253621630492442446415424016 349
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 39998740571245527452291803319556631510949049785235308954557577423691934785426 349
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 109068079101158560342890823425574755394321843500619765787246489225724548023474 346
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 45670916681001341893193433517548675421466889197986508902012605301190500493089 360
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 20612764111666279905970150296365833909192919973603343197113491321690953193091 359
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 9366725453845972272142682977390160134893623852316808984616435585779896223942 360
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 66662204439315761239521421540585368302744709967509544756581295184059020695428 323
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 81656021243929642165938683473056818973921644748908133577708245779697981829898 322
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 52250493346877893575511372758165757015042852367781954081465973215424467574404 325
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 76475072022551451627525074425381452918325651884744096175881120599689911861533 359
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16861715061736814862852529358705887371749501039521900987862218491143259542043 324
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 58043072667617093011902679091447554266138896250328917432323203315374913938 359
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 84702259427378587625378145426923971566919183851044328682901348906731516551757 323
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 54882738191779365648124175279593002442455635144643844980223717698772654881567 323
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3682494218880366068842337908454573946665441718043343958199707612500410142785 323
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 51294392534078280956691535166185688707748872049601883198993282887221301926555 324
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 74530756052916910824189807520785673193467600825999784830123799588476881122993 323
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 111417185353708672659388024986687762925726730071020525807438164830529311492205 324
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 36663309627096165623291560847132637582204138160676284991862352152353742943618 319
UVM_ERROR @ 15373.407287 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 15373.407287 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 57241876077142465086785192946877503860706636074087145445025949814375670505925 319
UVM_ERROR @ 16346.534312 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16346.534312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 39166239324051922816397262657060148434551389450801032179723479744444155979423 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 4452.148962 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4452.148962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---