Simulation Results: clkmgr

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.63 %
  • code
  • 98.06 %
  • assert
  • 94.92 %
  • func
  • 84.91 %
  • line
  • 98.96 %
  • branch
  • 98.65 %
  • cond
  • 93.50 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.300s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.820s 0.000us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.670s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.610s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.870s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.170s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.670s 0.000us 1 1 100.00
clkmgr_csr_aliasing 0.870s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.670s 0.000us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.820s 0.000us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.960s 0.000us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.700s 0.000us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.300s 0.000us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 5.420s 0.000us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.030s 0.000us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 5.420s 0.000us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 22.880s 0.000us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.720s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.080s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.080s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.820s 0.000us 1 1 100.00
clkmgr_csr_rw 0.670s 0.000us 1 1 100.00
clkmgr_csr_aliasing 0.870s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 1.370s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.820s 0.000us 1 1 100.00
clkmgr_csr_rw 0.670s 0.000us 1 1 100.00
clkmgr_csr_aliasing 0.870s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 1.370s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.640s 0.000us 0 1 0.00
clkmgr_tl_intg_err 1.400s 0.000us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.190s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.190s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.190s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.190s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.430s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.400s 0.000us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 5.420s 0.000us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.030s 0.000us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.190s 0.000us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.850s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.830s 0.000us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.710s 0.000us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.790s 0.000us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.850s 0.000us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.670s 0.000us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.640s 0.000us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.670s 0.000us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.670s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.640s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.100s 0.000us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 24.870s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 59975644489558742605180455715078519552086204413360836241497076088917556899762 83
UVM_ERROR @ 9589335 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 9589335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---