Simulation Results: flash_ctrl

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.44 %
  • code
  • 93.93 %
  • assert
  • 96.76 %
  • func
  • 95.63 %
  • line
  • 96.00 %
  • branch
  • 97.17 %
  • cond
  • 93.69 %
  • toggle
  • 97.78 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
98.46%
V2S
100.00%
V3
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 30.350s 0.000us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.410s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 16.290s 0.000us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.900s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 28.100s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 21.170s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.170s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.900s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 21.170s 0.000us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.270s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.240s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.220s 0.000us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 39.550s 0.000us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1244.240s 0.000us 1 1 100.00
flash_ctrl_hw_rma_reset 612.010s 0.000us 1 1 100.00
flash_ctrl_lcmgr_intg 5.530s 0.000us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1763.430s 0.000us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 169.170s 0.000us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.850s 0.000us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1671.610s 0.000us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 70.400s 0.000us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.390s 0.000us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.190s 0.000us 1 1 100.00
flash_ctrl_re_evict 19.470s 0.000us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 44.840s 0.000us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 44.840s 0.000us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 100.180s 0.000us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 10.350s 0.000us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 291.120s 0.000us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 347.230s 0.000us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 349.240s 0.000us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1006.220s 0.000us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.440s 0.000us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 126.960s 0.000us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.100s 0.000us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.640s 0.000us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 598.640s 0.000us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 86.770s 0.000us 1 1 100.00
flash_ctrl_otp_reset 52.490s 0.000us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1244.240s 0.000us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 130.790s 0.000us 1 1 100.00
flash_ctrl_intr_wr 51.290s 0.000us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 81.820s 0.000us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 125.360s 0.000us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 38.890s 0.000us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 39.450s 0.000us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.640s 0.000us 1 1 100.00
flash_ctrl_ro_derr 93.310s 0.000us 1 1 100.00
flash_ctrl_rw_derr 147.840s 0.000us 1 1 100.00
flash_ctrl_derr_detect 112.230s 0.000us 1 1 100.00
flash_ctrl_integrity 366.500s 0.000us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.450s 0.000us 1 1 100.00
flash_ctrl_ro_serr 77.070s 0.000us 1 1 100.00
flash_ctrl_rw_serr 137.700s 0.000us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 43.240s 0.000us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 70.390s 0.000us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 131.630s 0.000us 1 1 100.00
flash_ctrl_write_word_sweep 6.540s 0.000us 1 1 100.00
flash_ctrl_read_word_sweep 6.230s 0.000us 1 1 100.00
flash_ctrl_ro 17.660s 0.000us 0 1 0.00
flash_ctrl_rw 337.950s 0.000us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.630s 0.000us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 588.980s 0.000us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 51.970s 0.000us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.570s 0.000us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.420s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.810s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.810s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.290s 0.000us 1 1 100.00
flash_ctrl_csr_rw 7.900s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 21.170s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.470s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.290s 0.000us 1 1 100.00
flash_ctrl_csr_rw 7.900s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 21.170s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.470s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 31.350s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 31.350s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 31.350s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 31.350s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 57.930s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 350.780s 0.000us 1 1 100.00
flash_ctrl_sec_cm 1565.040s 0.000us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 350.780s 0.000us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 350.780s 0.000us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.700s 0.000us 1 1 100.00
flash_ctrl_wr_intg 6.310s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 30.350s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 52.490s 0.000us 1 1 100.00
flash_ctrl_disable 9.100s 0.000us 1 1 100.00
flash_ctrl_sec_info_access 33.880s 0.000us 1 1 100.00
flash_ctrl_connect 6.640s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.630s 0.000us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.900s 0.000us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 31.350s 0.000us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.900s 0.000us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 31.350s 0.000us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.900s 0.000us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 31.350s 0.000us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.100s 0.000us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.700s 0.000us 1 1 100.00
flash_ctrl_access_after_disable 6.550s 0.000us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.030s 0.000us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.100s 0.000us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 10.350s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 337.950s 0.000us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 137.700s 0.000us 1 1 100.00
flash_ctrl_rw_derr 147.840s 0.000us 1 1 100.00
flash_ctrl_integrity 366.500s 0.000us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1244.240s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1565.040s 0.000us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1565.040s 0.000us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1565.040s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1565.040s 0.000us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.000s 0.000us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 5.620s 0.000us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.980s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1565.040s 0.000us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1565.040s 0.000us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1565.040s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.260s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
flash_ctrl_basic_rw 85.040s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly
flash_ctrl_ro 97372356070530662425955723708285456864331592223089836220996801379551506947320 108
UVM_ERROR @ 114442.3 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 114442.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly
flash_ctrl_basic_rw 50676574508695030034113117232100107083044744173954197147298043419943183220104 196
UVM_ERROR @ 395162.3 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 395162.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---