Simulation Results: i2c

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.18 %
  • code
  • 81.14 %
  • assert
  • 96.19 %
  • func
  • 78.22 %
  • line
  • 96.01 %
  • branch
  • 91.84 %
  • cond
  • 85.31 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
91.84%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 13.070s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 7.510s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.920s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.770s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.260s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.700s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.770s 0.000us 1 1 100.00
i2c_csr_aliasing 1.700s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.750s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 891.340s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 7.520s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.720s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 82.790s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 106.370s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.860s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 14.860s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 4.520s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 65.820s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 7.660s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.830s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.610s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 27.310s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.790s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 3.220s 0.000us 1 1 100.00
i2c_target_intr_smoke 5.970s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.920s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.220s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 21.970s 0.000us 1 1 100.00
i2c_target_stress_rd 3.220s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 188.090s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.260s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 12.910s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.770s 0.000us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.450s 0.000us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 3.180s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.410s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 7.520s 0.000us 1 1 100.00
i2c_host_perf_precise 3.000s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 7.660s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.700s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 3.040s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 2.650s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.410s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.380s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.930s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.630s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.780s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.490s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.490s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.920s 0.000us 1 1 100.00
i2c_csr_rw 0.770s 0.000us 1 1 100.00
i2c_csr_aliasing 1.700s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.990s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.920s 0.000us 1 1 100.00
i2c_csr_rw 0.770s 0.000us 1 1 100.00
i2c_csr_aliasing 1.700s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.990s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.430s 0.000us 1 1 100.00
i2c_sec_cm 1.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.430s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 6.740s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 2.290s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 1.320s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 99134941781975127648730263626181691377862552155445707958021038696701113361410 86
UVM_ERROR @ 85027784 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 85027784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 62010845781214694812975631827259157475185185349249636247917715270443981290620 170
UVM_ERROR @ 57167756460 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 57167756460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 105887419189490324444253860886329393633603867987517504621549646108450860920007 85
UVM_ERROR @ 18273690 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 18273690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 63672356528199886216778439242393709179248610516166335726698977354168595605137 81
UVM_ERROR @ 25277204 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 25277204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 58685215458238505611509514045813354794014255917190837735488473778089263594480 84
UVM_ERROR @ 373588910 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 373588910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
i2c_target_unexp_stop 47833787020669107215059756603247658833101148183261548066170657631244642349817 79
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 228976631 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 228976631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 84052721443049412893943530386092519499444096008867535032716903598049134774645 87
UVM_ERROR @ 220068132 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 220068132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---