Simulation Results: lc_ctrl/volatile_unlock_enabled

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.55 %
  • code
  • 84.99 %
  • assert
  • 94.13 %
  • func
  • 92.53 %
  • line
  • 97.02 %
  • branch
  • 93.32 %
  • cond
  • 78.73 %
  • toggle
  • 87.47 %
  • FSM
  • 68.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.260s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.090s 0.000us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.880s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.480s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.910s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.880s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.230s 0.000us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.210s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.840s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.770s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.240s 0.000us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_ctrl_prog_failure 1.770s 0.000us 1 1 100.00
lc_ctrl_errors 8.240s 0.000us 1 1 100.00
lc_ctrl_security_escalation 6.300s 0.000us 1 1 100.00
lc_ctrl_jtag_state_failure 37.620s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.490s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 43.510s 0.000us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.940s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.720s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.490s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 43.510s 0.000us 1 1 100.00
lc_ctrl_jtag_access 4.480s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 17.240s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.800s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.450s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 20.280s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.580s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.270s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.500s 0.000us 1 1 100.00
lc_ctrl_jtag_alert_test 1.660s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.730s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.910s 0.000us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 78.430s 0.000us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.460s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.840s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.840s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.090s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.880s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.090s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.880s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.760s 0.000us 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.210s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.760s 0.000us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.760s 0.000us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.760s 0.000us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.760s 0.000us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.760s 0.000us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.760s 0.000us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.760s 0.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.170s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.760s 0.000us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.300s 0.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.230s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.720s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.250s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.250s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.870s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.120s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.120s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 36.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 16279802987811812198074051891904820751700655278661643054706273665682916380852 4567
UVM_ERROR @ 2109352533 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2109352533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---