Simulation Results: otbn

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.86 %
  • code
  • 93.47 %
  • assert
  • 88.50 %
  • func
  • 96.61 %
  • block
  • 98.99 %
  • line
  • 98.95 %
  • branch
  • 87.04 %
  • toggle
  • 90.47 %
  • FSM
  • 97.44 %
Validation stages
V1
90.91%
V2
78.95%
V2S
61.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 0.000us 1 1 100.00
single_binary 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 111.000s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 20.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 0 1 0.00
otbn_reset 4.000s 0.000us 0 1 0.00
multi_error 1 1 100.00
otbn_multi_err 63.000s 0.000us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 5.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
otbn_stress_all 4.000s 0.000us 0 1 0.00
lc_escalation 1 1 100.00
otbn_escalate 5.000s 0.000us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 0.000us 1 1 100.00
sw_errs_fatal_chk 0 1 0.00
otbn_sw_errs_fatal_chk 4.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 0.000us 1 1 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 3.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 0.000us 1 1 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 3.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 1 2 50.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
otbn_dmem_err 3.000s 0.000us 0 1 0.00
internal_integrity 1 4 25.00
otbn_alu_bignum_mod_err 4.000s 0.000us 0 1 0.00
otbn_controller_ispr_rdata_err 4.000s 0.000us 0 1 0.00
otbn_mac_bignum_acc_err 4.000s 0.000us 0 1 0.00
otbn_urnd_err 4.000s 0.000us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 0.000us 1 1 100.00
otbn_mem_gnt_acc_err 0 1 0.00
otbn_mem_gnt_acc_err 4.000s 0.000us 0 1 0.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
otbn_tl_intg_err 9.000s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 17.000s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 0.000us 1 1 100.00
sec_cm_data_mem_integrity 0 1 0.00
otbn_dmem_err 3.000s 0.000us 0 1 0.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 5.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
otbn_dmem_err 3.000s 0.000us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 5.000s 0.000us 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
otbn_dmem_err 3.000s 0.000us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 5.000s 0.000us 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 5.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
otbn_dmem_err 3.000s 0.000us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 5.000s 0.000us 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_data_reg_sw_sca 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 0.000us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 9.000s 0.000us 1 1 100.00
sec_cm_rnd_bus_consistency 0 1 0.00
otbn_rnd_sec_cm 4.000s 0.000us 0 1 0.00
sec_cm_rnd_rng_digest 0 1 0.00
otbn_rnd_sec_cm 4.000s 0.000us 0 1 0.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 6.000s 0.000us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 0 1 0.00
otbn_rf_bignum_intg_err 4.000s 0.000us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 0.000us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 0.000us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 0.000us 1 1 100.00
sec_cm_data_mem_sec_wipe 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_instruction_mem_sec_wipe 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_data_reg_sw_sec_wipe 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 5.000s 0.000us 0 1 0.00
sec_cm_ctrl_flow_count 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_ctrl_flow_sca 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_data_mem_sw_noaccess 0 1 0.00
otbn_sw_no_acc 5.000s 0.000us 0 1 0.00
sec_cm_key_sideload 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 84.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 4.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,152): Assertion NoModelErrs has failed
otbn_single 67583546091164130797548040598412370627094865840093463102174086616084247284980 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 30929440 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 30929440 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 30929440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_mac_bignum_acc_err 80143778813016991494723366210452808876116761806003281401867133065299022740175 115
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 6794220 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 6794220 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 6794220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 8273872191036936209393527863912030385370199981824803821465899719984209709444 114
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 22745754 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 22745754 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 22745754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all 47162957049319032978260369350202732853794123334113764577846146243045848842733 151
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 15995514 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 15995514 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 15995514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sw_no_acc 1309184852010994570340413069261502286058704779334905069406931264493068020402 115
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 35414537 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 35414537 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 35414537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value.
otbn_multi 39255549140734600418338714921300712085670936800518766048829650095544300950362 155
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 119563496 PS + 23) Sampled value (27705693502268022) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
UVM_FATAL @ 119563496 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.subv'
UVM_INFO @ 119563496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_reset 44456098824491555614074715116781145721301182943671231046948764835470874674485 115
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 7595560 PS + 25) Sampled value (7092657458986120813) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
UVM_FATAL @ 7595560 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.addvm'
UVM_INFO @ 7595560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_dmem_err 44478051326471899436698161570393312105950460260614763323303331069243359011417 117
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 40157674 PS + 25) Sampled value (27705693535367275) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
UVM_FATAL @ 40157674 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.unpk'
UVM_INFO @ 40157674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_alu_bignum_mod_err 54248189671298856076608632236630255552238188669231797843798508068547613420553 114
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 17834162 PS + 25) Sampled value (27705693518851633) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
UVM_FATAL @ 17834162 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn1'
UVM_INFO @ 17834162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_controller_ispr_rdata_err 82468383232644069667231340925450355125835795579779074596432261499137409137444 111
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 4031740 PS + 23) Sampled value (7092657458986120813) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
UVM_FATAL @ 4031740 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.addvm'
UVM_INFO @ 4031740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rnd_sec_cm 100793165334494516972329339947206150592937840536361733974844137784902338806584 105
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 6618519 PS + 25) Sampled value (108225365239926) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
UVM_FATAL @ 6618519 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.shv'
UVM_INFO @ 6618519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_mem_gnt_acc_err 43182409892769944119726217288798566145769712978993093036329140616784733372014 114
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 4379184 PS + 25) Sampled value (27705693518851634) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
UVM_FATAL @ 4379184 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn2'
UVM_INFO @ 4379184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 34958023942446161905184701013783421756730399426993378880697560135394084014296 113
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 16168814 PS + 31) Sampled value (27705693450625899) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4200_1.cur_cp) is an illegal value.
UVM_FATAL @ 16168814 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.pack'
UVM_INFO @ 16168814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 8924943314714217589402651331337667035088718349123968924286204842730322428024 147
UVM_FATAL @ 29517671 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 29517671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_sw_errs_fatal_chk 58831888593249688311877015261929529228104239761170035889764431993950526329679 114
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 44698074 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 44698074 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 44698074 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 44698074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---