Simulation Results

Simulation Results: pwrmgr

10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.46 %

code
94.17 %

assert
95.82 %

func
96.38 %

line
98.76 %

branch
94.85 %

cond
93.21 %

toggle
90.02 %

FSM
94.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		47.06%
V3		50.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	pwrmgr_smoke	0.660s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	pwrmgr_csr_hw_reset	0.600s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	pwrmgr_csr_rw	0.590s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	pwrmgr_csr_bit_bash	1.250s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	pwrmgr_csr_aliasing	0.710s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	pwrmgr_csr_mem_rw_with_rand_reset	0.650s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	pwrmgr_csr_rw	0.590s	0.000us	1	1	100.00
	pwrmgr_csr_aliasing	0.710s	0.000us	1	1	100.00

22/22 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wakeup				1	1	100.00
	pwrmgr_wakeup	0.810s	0.000us	1	1	100.00
control_clks				1	1	100.00
	pwrmgr_wakeup	0.810s	0.000us	1	1	100.00
aborted_low_power				2	2	100.00
	pwrmgr_aborted_low_power	0.680s	0.000us	1	1	100.00
	pwrmgr_lowpower_invalid	0.640s	0.000us	1	1	100.00
reset				2	2	100.00
	pwrmgr_reset	0.780s	0.000us	1	1	100.00
	pwrmgr_reset_invalid	0.750s	0.000us	1	1	100.00
main_power_glitch_reset				1	1	100.00
	pwrmgr_reset	0.780s	0.000us	1	1	100.00
reset_wakeup_race				1	1	100.00
	pwrmgr_wakeup_reset	0.580s	0.000us	1	1	100.00
lowpower_wakeup_race				1	1	100.00
	pwrmgr_lowpower_wakeup_race	0.610s	0.000us	1	1	100.00
disable_rom_integrity_check				1	1	100.00
	pwrmgr_disable_rom_integrity_check	0.870s	0.000us	1	1	100.00
stress_all				1	1	100.00
	pwrmgr_stress_all	3.270s	0.000us	1	1	100.00
intr_test				1	1	100.00
	pwrmgr_intr_test	0.610s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	pwrmgr_tl_errors	1.000s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	pwrmgr_tl_errors	1.000s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.600s	0.000us	1	1	100.00
	pwrmgr_csr_rw	0.590s	0.000us	1	1	100.00
	pwrmgr_csr_aliasing	0.710s	0.000us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.700s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.600s	0.000us	1	1	100.00
	pwrmgr_csr_rw	0.590s	0.000us	1	1	100.00
	pwrmgr_csr_aliasing	0.710s	0.000us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.700s	0.000us	1	1	100.00

V2S

8/17 passed

47.06 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	2	0.00
	pwrmgr_sec_cm	0.650s	0.000us	0	1	0.00
	pwrmgr_tl_intg_err	0.580s	0.000us	0	1	0.00
prim_count_check				0	1	0.00
	pwrmgr_sec_cm	0.650s	0.000us	0	1	0.00
prim_fsm_check				0	1	0.00
	pwrmgr_sec_cm	0.650s	0.000us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	pwrmgr_tl_intg_err	0.580s	0.000us	0	1	0.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.960s	0.000us	1	1	100.00
sec_cm_rom_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_wakeup_reset	0.580s	0.000us	1	1	100.00
sec_cm_rstmgr_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.690s	0.000us	1	1	100.00
sec_cm_esc_rx_clk_bkgn_chk				0	1	0.00
	pwrmgr_esc_clk_rst_malfunc	0.540s	0.000us	0	1	0.00
sec_cm_esc_rx_clk_local_esc				0	1	0.00
	pwrmgr_sec_cm	0.650s	0.000us	0	1	0.00
sec_cm_fsm_sparse				0	1	0.00
	pwrmgr_sec_cm	0.650s	0.000us	0	1	0.00
sec_cm_fsm_terminal				0	1	0.00
	pwrmgr_sec_cm	0.650s	0.000us	0	1	0.00
sec_cm_ctrl_flow_global_esc				1	1	100.00
	pwrmgr_global_esc	0.590s	0.000us	1	1	100.00
sec_cm_main_pd_rst_local_esc				1	1	100.00
	pwrmgr_glitch	0.550s	0.000us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	pwrmgr_sec_cm_ctrl_config_regwen	0.610s	0.000us	1	1	100.00
sec_cm_wakeup_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.590s	0.000us	1	1	100.00
sec_cm_reset_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.590s	0.000us	1	1	100.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
escalation_timeout				0	1	0.00
	pwrmgr_escalation_timeout	0.660s	0.000us	0	1	0.00
stress_all_with_rand_reset				1	1	100.00
	pwrmgr_stress_all_with_rand_reset	2.310s	0.000us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
	pwrmgr_esc_clk_rst_malfunc	58240290038033348204059870935612945945688613094921371018629378766671949763403	75	UVM_ERROR @ 8805352 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A UVM_INFO @ 8805352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_escalation_timeout	109509915536460525199163791751186242580232942149797860849125943495464082942584	75	UVM_ERROR @ 92761467 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A UVM_INFO @ 92761467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
	pwrmgr_sec_cm	71173025374902627964808686649313731913710620101959130023451793555945521427894	79	UVM_ERROR @ 15181293 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 15181293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_tl_intg_err	109129634576033475539239848723956690166334715097043786402993566303566561368122	82	UVM_ERROR @ 9007418 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 9007418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---