Simulation Results: spi_device/2p

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.29 %
  • code
  • 93.73 %
  • assert
  • 94.62 %
  • func
  • 64.53 %
  • line
  • 99.12 %
  • branch
  • 98.35 %
  • cond
  • 96.20 %
  • toggle
  • 87.74 %
  • FSM
  • 87.23 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 44.480s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.800s 0.000us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.090s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 26.430s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.230s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.810s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.090s 0.000us 1 1 100.00
spi_device_csr_aliasing 5.230s 0.000us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.640s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.390s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.820s 0.000us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.940s 0.000us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.960s 0.000us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.930s 0.000us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.930s 0.000us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 12.960s 0.000us 1 1 100.00
spi_device_tpm_sts_read 0.850s 0.000us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 2.510s 0.000us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.990s 0.000us 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.940s 0.000us 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.940s 0.000us 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.240s 0.000us 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.240s 0.000us 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.240s 0.000us 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.240s 0.000us 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.240s 0.000us 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.870s 0.000us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 2.880s 0.000us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 2.880s 0.000us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 2.880s 0.000us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 9.210s 0.000us 1 1 100.00
spi_device_read_buffer_direct 12.510s 0.000us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 2.880s 0.000us 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 199.000s 0.000us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.760s 0.000us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.760s 0.000us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 44.480s 0.000us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 34.000s 0.000us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.310s 0.000us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.670s 0.000us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.690s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.900s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.900s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 0.000us 1 1 100.00
spi_device_csr_rw 1.090s 0.000us 1 1 100.00
spi_device_csr_aliasing 5.230s 0.000us 1 1 100.00
spi_device_same_csr_outstanding 2.150s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 0.000us 1 1 100.00
spi_device_csr_rw 1.090s 0.000us 1 1 100.00
spi_device_csr_aliasing 5.230s 0.000us 1 1 100.00
spi_device_same_csr_outstanding 2.150s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 10.510s 0.000us 1 1 100.00
spi_device_sec_cm 1.060s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 10.510s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 36.040s 0.000us 1 1 100.00