Simulation Results: sram_ctrl/ret

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.10 %
  • code
  • 90.00 %
  • assert
  • 95.23 %
  • func
  • 94.06 %
  • line
  • 97.40 %
  • branch
  • 94.70 %
  • cond
  • 91.06 %
  • toggle
  • 90.66 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.050s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.740s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.610s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.650s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.790s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.650s 0.000us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.050s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.220s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 675.690s 0.000us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 113.400s 0.000us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 15.850s 0.000us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 473.410s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.740s 0.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 700.410s 0.000us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.510s 0.000us 1 1 100.00
sram_ctrl_partial_access_b2b 219.880s 0.000us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 32.380s 0.000us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.160s 0.000us 1 1 100.00
sram_ctrl_throughput_w_readback 38.670s 0.000us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 980.170s 0.000us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.670s 0.000us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 481.900s 0.000us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.670s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.040s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.040s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.650s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.690s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.650s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.690s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.580s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.620s 0.000us 0 1 0.00
sram_ctrl_tl_intg_err 1.140s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.620s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.140s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 980.170s 0.000us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 980.170s 0.000us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 700.410s 0.000us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 700.410s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 700.410s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.740s 0.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.870s 0.000us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.580s 0.000us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 0.690s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.050s 0.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.050s 0.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 700.410s 0.000us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.620s 0.000us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.740s 0.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.620s 0.000us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.620s 0.000us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.050s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.620s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 87.780s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 104844608099964532165536280966439047897741267624882555211315912228503695280547 98
UVM_ERROR @ 26166885 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x34)
UVM_INFO @ 26166885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 37065203653003896754388916526740359865623258479345261537195118400004549333243 100
UVM_ERROR @ 2659922 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2659922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---