Simulation Results: sysrst_ctrl

 
10/03/2026 17:17:01 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.82 %
  • code
  • 92.57 %
  • assert
  • 93.58 %
  • func
  • 59.30 %
  • line
  • 97.19 %
  • branch
  • 97.37 %
  • cond
  • 95.23 %
  • toggle
  • 100.00 %
  • FSM
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.830s 0.000us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.460s 0.000us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.860s 0.000us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.870s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 11.480s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.380s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 15.090s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.770s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.860s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.380s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.770s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 27.880s 0.000us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 31.090s 0.000us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 8.490s 0.000us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.580s 0.000us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.160s 0.000us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.330s 0.000us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.370s 0.000us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.840s 0.000us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.210s 0.000us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 82.080s 0.000us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 20.360s 0.000us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.780s 0.000us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 0.900s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.980s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.980s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.480s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 4.380s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.770s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.170s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.480s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 4.380s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.770s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.170s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 41.210s 0.000us 1 1 100.00
sysrst_ctrl_tl_intg_err 42.270s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 42.270s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.530s 0.000us 1 1 100.00