Simulation Results: alert_handler

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.30 %
  • code
  • 93.29 %
  • assert
  • 98.42 %
  • func
  • 82.19 %
  • line
  • 99.74 %
  • branch
  • 99.80 %
  • cond
  • 94.76 %
  • toggle
  • 93.13 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 2.820s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.130s 0.000us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.040s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 253.160s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 164.910s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.660s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.040s 0.000us 1 1 100.00
alert_handler_csr_aliasing 164.910s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 51.240s 0.000us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 11.300s 0.000us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1018.070s 0.000us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 18.900s 0.000us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 2.820s 0.000us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 12.720s 0.000us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 12.090s 0.000us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 140.660s 0.000us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 756.140s 0.000us 1 1 100.00
alert_handler_lpg_stub_clk 1680.790s 0.000us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 829.460s 0.000us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 25.220s 0.000us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.940s 0.000us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.150s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 10.780s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 10.780s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.130s 0.000us 1 1 100.00
alert_handler_csr_rw 4.040s 0.000us 1 1 100.00
alert_handler_csr_aliasing 164.910s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 17.030s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.130s 0.000us 1 1 100.00
alert_handler_csr_rw 4.040s 0.000us 1 1 100.00
alert_handler_csr_aliasing 164.910s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 17.030s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 186.950s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 186.950s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 186.950s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 186.950s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 372.660s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_tl_intg_err 15.090s 0.000us 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 15.090s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 186.950s 0.000us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 2.820s 0.000us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 2.820s 0.000us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 2.820s 0.000us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 2.820s 0.000us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 18.900s 0.000us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 756.140s 0.000us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 18.900s 0.000us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1018.070s 0.000us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1018.070s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 21.890s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 178.360s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 110664474052602106916685059256697671579036382743753242998232477232443816601580 120
UVM_ERROR @ 12127000101 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 12127000101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---