Simulation Results: flash_ctrl

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.43 %
  • code
  • 93.85 %
  • assert
  • 96.67 %
  • func
  • 95.76 %
  • line
  • 95.95 %
  • branch
  • 97.15 %
  • cond
  • 93.55 %
  • toggle
  • 97.58 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
98.46%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 20.130s 0.000us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 8.290s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 18.470s 0.000us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 6.020s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 50.730s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 37.150s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 7.700s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 6.020s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 37.150s 0.000us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.180s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 7.540s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.490s 0.000us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 20.980s 0.000us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1279.930s 0.000us 1 1 100.00
flash_ctrl_hw_rma_reset 634.340s 0.000us 1 1 100.00
flash_ctrl_lcmgr_intg 5.410s 0.000us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1110.330s 0.000us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 301.140s 0.000us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.450s 0.000us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1881.500s 0.000us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 103.790s 0.000us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 21.990s 0.000us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.950s 0.000us 1 1 100.00
flash_ctrl_re_evict 22.040s 0.000us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 127.790s 0.000us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 127.790s 0.000us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 173.670s 0.000us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 25.230s 0.000us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 335.980s 0.000us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 535.150s 0.000us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 290.940s 0.000us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 672.480s 0.000us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.560s 0.000us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 102.800s 0.000us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.410s 0.000us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.150s 0.000us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 23.440s 0.000us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 77.710s 0.000us 1 1 100.00
flash_ctrl_otp_reset 50.940s 0.000us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1279.930s 0.000us 1 1 100.00
interrupts 3 4 75.00
flash_ctrl_intr_rd 129.450s 0.000us 1 1 100.00
flash_ctrl_intr_wr 54.050s 0.000us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 97.440s 0.000us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 0.000s 0.000us 0 1 0.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 38.660s 0.000us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.630s 0.000us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.500s 0.000us 1 1 100.00
flash_ctrl_ro_derr 92.930s 0.000us 1 1 100.00
flash_ctrl_rw_derr 146.240s 0.000us 1 1 100.00
flash_ctrl_derr_detect 93.290s 0.000us 1 1 100.00
flash_ctrl_integrity 388.960s 0.000us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.550s 0.000us 1 1 100.00
flash_ctrl_ro_serr 77.190s 0.000us 1 1 100.00
flash_ctrl_rw_serr 152.430s 0.000us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 43.180s 0.000us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 69.530s 0.000us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 156.510s 0.000us 1 1 100.00
flash_ctrl_write_word_sweep 7.230s 0.000us 1 1 100.00
flash_ctrl_read_word_sweep 8.400s 0.000us 1 1 100.00
flash_ctrl_ro 68.290s 0.000us 1 1 100.00
flash_ctrl_rw 390.350s 0.000us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.930s 0.000us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 623.500s 0.000us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 48.040s 0.000us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.750s 0.000us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.540s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.820s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.820s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.470s 0.000us 1 1 100.00
flash_ctrl_csr_rw 6.020s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 37.150s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.430s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.470s 0.000us 1 1 100.00
flash_ctrl_csr_rw 6.020s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 37.150s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.430s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.760s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 9.760s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.760s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 9.760s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 35.310s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 176.650s 0.000us 1 1 100.00
flash_ctrl_sec_cm 1596.970s 0.000us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 176.650s 0.000us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 176.650s 0.000us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.470s 0.000us 1 1 100.00
flash_ctrl_wr_intg 6.460s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 20.130s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 50.940s 0.000us 1 1 100.00
flash_ctrl_disable 9.410s 0.000us 1 1 100.00
flash_ctrl_sec_info_access 38.530s 0.000us 1 1 100.00
flash_ctrl_connect 5.150s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.880s 0.000us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.020s 0.000us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.760s 0.000us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.020s 0.000us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.760s 0.000us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.020s 0.000us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.760s 0.000us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.410s 0.000us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.470s 0.000us 1 1 100.00
flash_ctrl_access_after_disable 6.340s 0.000us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.000s 0.000us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.410s 0.000us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 25.230s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 390.350s 0.000us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 152.430s 0.000us 1 1 100.00
flash_ctrl_rw_derr 146.240s 0.000us 1 1 100.00
flash_ctrl_integrity 388.960s 0.000us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1279.930s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1596.970s 0.000us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1596.970s 0.000us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1596.970s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1596.970s 0.000us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.900s 0.000us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 8.550s 0.000us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.080s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1596.970s 0.000us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1596.970s 0.000us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1596.970s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.140s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 349.600s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes
flash_ctrl_intr_wr_slow_flash 85208411577198054471729059568638830691617655509852107855738286589094834842868 None
Job timed out after 60 minutes