| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 0.880s | 0.000us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 0.950s | 0.000us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.020s | 0.000us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.270s | 0.000us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.690s | 0.000us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.660s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 2.180s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 0.850s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.120s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 0.660s | 0.000us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.850s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 0.860s | 0.000us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 0.660s | 0.000us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.910s | 0.000us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 0.780s | 0.000us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 2.140s | 0.000us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 1.670s | 0.000us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 4.920s | 0.000us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 3.490s | 0.000us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 1.000s | 0.000us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| gpio_stress_all | 17.650s | 0.000us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.540s | 0.000us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.660s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.220s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.220s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.660s | 0.000us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.700s | 0.000us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.850s | 0.000us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.690s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.660s | 0.000us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.700s | 0.000us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.850s | 0.000us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.690s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_sec_cm | 0.810s | 0.000us | 1 | 1 | 100.00 | |
| gpio_tl_intg_err | 0.900s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 0.900s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.650s | 0.000us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 2.820s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* | ||||
| gpio_stress_all_with_rand_reset | 53847010603569991605727414654665248480478011603933591480491326714317431550563 | 78 |
UVM_FATAL @ 404529356 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 404529356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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