Simulation Results: otbn

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.08 %
  • code
  • 92.87 %
  • assert
  • 88.92 %
  • func
  • 97.46 %
  • block
  • 99.02 %
  • line
  • 98.98 %
  • branch
  • 87.36 %
  • toggle
  • 90.26 %
  • FSM
  • 94.87 %
Validation stages
V1
90.91%
V2
68.42%
V2S
61.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 0.000us 1 1 100.00
single_binary 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 0.000us 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 93.000s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 20.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 0 1 0.00
otbn_reset 6.000s 0.000us 0 1 0.00
multi_error 1 1 100.00
otbn_multi_err 43.000s 0.000us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 5.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
otbn_stress_all 4.000s 0.000us 0 1 0.00
lc_escalation 0 1 0.00
otbn_escalate 7.000s 0.000us 0 1 0.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 4.000s 0.000us 0 1 0.00
sw_errs_fatal_chk 0 1 0.00
otbn_sw_errs_fatal_chk 5.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 0.000us 1 1 100.00
otbn_csr_rw 4.000s 0.000us 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 5.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 0.000us 1 1 100.00
otbn_csr_rw 4.000s 0.000us 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 5.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
otbn_dmem_err 11.000s 0.000us 1 1 100.00
internal_integrity 2 4 50.00
otbn_alu_bignum_mod_err 5.000s 0.000us 0 1 0.00
otbn_controller_ispr_rdata_err 7.000s 0.000us 1 1 100.00
otbn_mac_bignum_acc_err 4.000s 0.000us 0 1 0.00
otbn_urnd_err 5.000s 0.000us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 0.000us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 0.000us 1 1 100.00
otbn_non_sec_partial_wipe 0 1 0.00
otbn_partial_wipe 6.000s 0.000us 0 1 0.00
tl_intg_err 2 2 100.00
otbn_tl_intg_err 10.000s 0.000us 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 18.000s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 0.000us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 11.000s 0.000us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_global_esc 0 1 0.00
otbn_escalate 7.000s 0.000us 0 1 0.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
otbn_dmem_err 11.000s 0.000us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 0.000us 0 1 0.00
otbn_illegal_mem_acc 5.000s 0.000us 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
otbn_dmem_err 11.000s 0.000us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 0.000us 0 1 0.00
otbn_illegal_mem_acc 5.000s 0.000us 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 0 1 0.00
otbn_escalate 7.000s 0.000us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 0.000us 1 1 100.00
otbn_dmem_err 11.000s 0.000us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 0.000us 0 1 0.00
otbn_illegal_mem_acc 5.000s 0.000us 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_data_reg_sw_sca 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
otbn_ctrl_redun 5.000s 0.000us 0 1 0.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 0.000us 1 1 100.00
sec_cm_rnd_bus_consistency 0 1 0.00
otbn_rnd_sec_cm 8.000s 0.000us 0 1 0.00
sec_cm_rnd_rng_digest 0 1 0.00
otbn_rnd_sec_cm 8.000s 0.000us 0 1 0.00
sec_cm_rf_base_data_reg_sw_integrity 0 1 0.00
otbn_rf_base_intg_err 5.000s 0.000us 0 1 0.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 6.000s 0.000us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 4.000s 0.000us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 4.000s 0.000us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 0.000us 1 1 100.00
sec_cm_data_mem_sec_wipe 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_instruction_mem_sec_wipe 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_data_reg_sw_sec_wipe 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 5.000s 0.000us 0 1 0.00
sec_cm_ctrl_flow_count 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_ctrl_flow_sca 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_data_mem_sw_noaccess 0 1 0.00
otbn_sw_no_acc 4.000s 0.000us 0 1 0.00
sec_cm_key_sideload 0 1 0.00
otbn_single 5.000s 0.000us 0 1 0.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 91.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 4.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,152): Assertion NoModelErrs has failed
otbn_single 79142537663213815739563612885358415979802930397090409619924835262942591724645 127
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 22150651 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 22150651 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 22150651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_reset 60346078065142260971611236455282858964312778062813384404262125496979888373122 131
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 10132406 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 10132406 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 10132406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 34827516709862043577997352808822502737466990572491860379070781507649048871073 120
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 20093270 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 20093270 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 20093270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_mac_bignum_acc_err 100012511505883998548852733660353016800161887863846740607917190543641555811747 114
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 60202667 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 60202667 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 60202667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 196109658962748660243325091564269354055192182841257366961842397289816911227 151
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 4805441 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4805441 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4805441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 27791547628677465240812182300716565953953478370621329414774364783724329852536 110
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 13678718 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 13678718 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 13678718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sw_no_acc 54685213647706421081544804962459050915159949986409671393573162450699297889555 114
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 7392103 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 7392103 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 7392103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value.
otbn_multi 33189815723410390399036771419570807178490463207187688377784282024094872948562 154
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 20080131 PS + 25) Sampled value (27705693450625899) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 20080131 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.pack'
UVM_INFO @ 20080131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_alu_bignum_mod_err 19981460290200557705025233287114473123204459377102503771493069551190592879545 110
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 58010687 PS + 27) Sampled value (108225365239926) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 58010687 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.shv'
UVM_INFO @ 58010687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_base_intg_err 44232809289045618696100320114023563036128980398087961962239868042536084934673 107
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 7311648 PS + 23) Sampled value (27705693502268022) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 7311648 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.subv'
UVM_INFO @ 7311648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all 75012040365138084290194770348455287461147345886022734641002558621139008349936 143
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 9190440 PS + 25) Sampled value (27705693518851633) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 9190440 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn1'
UVM_INFO @ 9190440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sw_errs_fatal_chk 63166661515546453377037502144047579450701872056252215405788443589965800700652 113
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 16950643 PS + 25) Sampled value (27705693518851634) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 16950643 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn2'
UVM_INFO @ 16950643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rnd_sec_cm 38392221672537310497117268331107837925386661843263274152423924971295111983753 114
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 255171059 PS + 30) Sampled value (27705693535367275) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 255171059 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.unpk'
UVM_INFO @ 255171059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_ctrl_redun 46417606883768690341276744693621496804338614260636812355067906381924767566372 111
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 9031469 PS + 32) Sampled value (27705693518851634) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 9031469 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn2'
UVM_INFO @ 9031469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 73883248847986366827091267202572535728307601177351843612123452884266253109410 107
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 85269814 PS + 25) Sampled value (27705693502268022) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 85269814 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.subv'
UVM_INFO @ 85269814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 90907985759841680084688426602007777919654341248105071376968812407138083234449 114
UVM_ERROR @ 8073633 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (1 [0x1] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 8073633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---