Simulation Results: otp_ctrl

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.65 %
  • code
  • 79.25 %
  • assert
  • 93.28 %
  • func
  • 78.43 %
  • line
  • 88.77 %
  • branch
  • 83.45 %
  • cond
  • 90.43 %
  • toggle
  • 88.63 %
  • FSM
  • 44.97 %
Validation stages
V1
90.91%
V2
96.00%
V2S
98.21%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.160s 0.000us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.540s 0.000us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.250s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 2.830s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.950s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.520s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.250s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 4.950s 0.000us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.270s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.830s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.060s 0.000us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.190s 0.000us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 20.280s 0.000us 1 1 100.00
otp_ctrl_check_fail 3.390s 0.000us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.980s 0.000us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 3.270s 0.000us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 5.660s 0.000us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 14.730s 0.000us 1 1 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.870s 0.000us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 13.400s 0.000us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 11.080s 0.000us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 258.400s 0.000us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.210s 0.000us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.800s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.680s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.680s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.540s 0.000us 1 1 100.00
otp_ctrl_csr_rw 1.250s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 4.950s 0.000us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.540s 0.000us 1 1 100.00
otp_ctrl_csr_rw 1.250s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 4.950s 0.000us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 24.010s 0.000us 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 24.010s 0.000us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.000s 0.000us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.000s 0.000us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
otp_ctrl_macro_errs 13.400s 0.000us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
otp_ctrl_macro_errs 13.400s 0.000us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.470s 0.000us 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.190s 0.000us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.390s 0.000us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 3.270s 0.000us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 3.270s 0.000us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 3.270s 0.000us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 3.270s 0.000us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 3.270s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.000s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 3.270s 0.000us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.000s 0.000us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 104.020s 0.000us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.980s 0.000us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.000s 0.000us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.000s 0.000us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 13.400s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.380s 0.000us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.410s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_csr_mem_rw_with_rand_reset 13248783923315805064212578501823600263700724161041912746564617858704697947027 92
UVM_ERROR @ 28277077 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28277077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49429520495683083666480189051161658535497679857291900982995946505148712322647 97
UVM_ERROR @ 29331337 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 29331337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_check_fail 86762068453953530966473043996558818796580126471072172637359735291591915876242 1766
UVM_ERROR @ 454688202 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 454688202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---