Simulation Results: pwm

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.36 %
  • code
  • 96.01 %
  • assert
  • 98.00 %
  • func
  • 92.08 %
  • block
  • 98.85 %
  • line
  • 99.21 %
  • branch
  • 97.95 %
  • toggle
  • 90.87 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwm_smoke 4.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
pwm_csr_hw_reset 1.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
pwm_csr_rw 1.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
pwm_csr_bit_bash 3.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
pwm_csr_aliasing 2.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwm_csr_mem_rw_with_rand_reset 1.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwm_csr_rw 1.000s 0.000us 1 1 100.00
pwm_csr_aliasing 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 1 1 100.00
pwm_rand_output 29.000s 0.000us 1 1 100.00
pulse 1 1 100.00
pwm_rand_output 29.000s 0.000us 1 1 100.00
blink 1 1 100.00
pwm_rand_output 29.000s 0.000us 1 1 100.00
heartbeat 1 1 100.00
pwm_rand_output 29.000s 0.000us 1 1 100.00
resolution 1 1 100.00
pwm_rand_output 29.000s 0.000us 1 1 100.00
multi_channel 1 1 100.00
pwm_rand_output 29.000s 0.000us 1 1 100.00
polarity 1 1 100.00
pwm_rand_output 29.000s 0.000us 1 1 100.00
phase 2 2 100.00
pwm_rand_output 29.000s 0.000us 1 1 100.00
pwm_phase 35.000s 0.000us 1 1 100.00
lowpower 1 1 100.00
pwm_rand_output 29.000s 0.000us 1 1 100.00
perf 1 1 100.00
pwm_perf 34.000s 0.000us 1 1 100.00
regwen 0 1 0.00
pwm_regwen 49.000s 0.000us 0 1 0.00
stress_all 1 1 100.00
pwm_stress_all 106.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
pwm_alert_test 1.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwm_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwm_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwm_csr_hw_reset 1.000s 0.000us 1 1 100.00
pwm_csr_rw 1.000s 0.000us 1 1 100.00
pwm_csr_aliasing 2.000s 0.000us 1 1 100.00
pwm_same_csr_outstanding 2.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwm_csr_hw_reset 1.000s 0.000us 1 1 100.00
pwm_csr_rw 1.000s 0.000us 1 1 100.00
pwm_csr_aliasing 2.000s 0.000us 1 1 100.00
pwm_same_csr_outstanding 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwm_sec_cm 1.000s 0.000us 1 1 100.00
pwm_tl_intg_err 2.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwm_tl_intg_err 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 1 1 100.00
pwm_heartbeat_wrap 25.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.invert (addr=*)
pwm_regwen 28690579090334280368114747009970317554644996856229976734610700527640263618418 93
UVM_FATAL @ 23874813393 ps: (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.invert (addr=0x2fd73f90)
UVM_INFO @ 23874813393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---