Simulation Results: rom_ctrl/32kb

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 93.52 %
  • assert
  • 96.80 %
  • func
  • 96.66 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 95.99 %
  • toggle
  • 99.57 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
58.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.480s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.840s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.200s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.530s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.060s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.860s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.200s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 5.060s 0.000us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.030s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.850s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.860s 0.000us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 20.680s 0.000us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.350s 0.000us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.840s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.540s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.540s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.840s 0.000us 1 1 100.00
rom_ctrl_csr_rw 3.200s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 5.060s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.880s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.840s 0.000us 1 1 100.00
rom_ctrl_csr_rw 3.200s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 5.060s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.880s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.510s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 102.200s 0.000us 1 1 100.00
rom_ctrl_tl_intg_err 43.380s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 102.200s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 102.200s 0.000us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 102.200s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 102.200s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.480s 0.000us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.480s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.480s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 43.380s 0.000us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 7.350s 0.000us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 11.330s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.510s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 102.200s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 58.520s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 106160163169970427964649698018169743425600478408889519290511704302907517335726 85
UVM_ERROR @ 651847686 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 651847686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---