Simulation Results: sram_ctrl/main

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.70 %
  • code
  • 85.50 %
  • assert
  • 95.55 %
  • func
  • 94.06 %
  • line
  • 96.25 %
  • branch
  • 92.82 %
  • cond
  • 90.58 %
  • toggle
  • 90.71 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 35.210s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.740s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.710s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.540s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.300s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.710s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 0.000us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 95.610s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 56.510s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 752.650s 0.000us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 143.090s 0.000us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 971.050s 0.000us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 725.670s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 42.350s 0.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 530.190s 0.000us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 17.660s 0.000us 1 1 100.00
sram_ctrl_partial_access_b2b 408.420s 0.000us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 46.080s 0.000us 1 1 100.00
sram_ctrl_throughput_w_partial_write 56.360s 0.000us 1 1 100.00
sram_ctrl_throughput_w_readback 23.100s 0.000us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 158.000s 0.000us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.490s 0.000us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2188.470s 0.000us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.810s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.750s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.750s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.710s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.880s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.710s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.880s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.980s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.890s 0.000us 0 1 0.00
sram_ctrl_tl_intg_err 1.610s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.890s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.610s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 158.000s 0.000us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 158.000s 0.000us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.710s 0.000us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 530.190s 0.000us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 530.190s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 530.190s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 42.350s 0.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.280s 0.000us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.980s 0.000us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3.540s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 35.210s 0.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 35.210s 0.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 530.190s 0.000us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.890s 0.000us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 42.350s 0.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.890s 0.000us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.890s 0.000us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 35.210s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.890s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 20.860s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 62264842511913027883315728251221445532855770956237934791558847593229774589569 98
UVM_ERROR @ 3010323568 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7a) != exp (0x6d)
UVM_INFO @ 3010323568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 11761498343024085000583109848520389533051955675485131965298650082694691482422 99
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 2258104 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 2258104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---