Simulation Results: sram_ctrl/ret

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.61 %
  • code
  • 90.02 %
  • assert
  • 95.23 %
  • func
  • 92.58 %
  • line
  • 97.68 %
  • branch
  • 95.45 %
  • cond
  • 90.21 %
  • toggle
  • 90.59 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.960s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.860s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.340s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.090s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 0.000us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.800s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.630s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 677.950s 0.000us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 261.900s 0.000us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 29.300s 0.000us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 96.360s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.040s 0.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 560.840s 0.000us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 14.660s 0.000us 1 1 100.00
sram_ctrl_partial_access_b2b 211.940s 0.000us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 35.370s 0.000us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.740s 0.000us 1 1 100.00
sram_ctrl_throughput_w_readback 14.720s 0.000us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 511.840s 0.000us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.960s 0.000us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2516.050s 0.000us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.710s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.260s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.260s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.860s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.860s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.700s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.910s 0.000us 0 1 0.00
sram_ctrl_tl_intg_err 1.750s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.910s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.750s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 511.840s 0.000us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 511.840s 0.000us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 560.840s 0.000us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 560.840s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 560.840s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.040s 0.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.210s 0.000us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.700s 0.000us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.960s 0.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.960s 0.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 560.840s 0.000us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.910s 0.000us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.040s 0.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.910s 0.000us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.910s 0.000us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.960s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.910s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
sram_ctrl_stress_all_with_rand_reset 56.560s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
sram_ctrl_stress_all_with_rand_reset 82011014763240156823267595909689329248809733712431361199799581372427706436119 250
UVM_ERROR @ 1236477037 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1236477037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 29134275944627319911594299320626144805012931690397998770825136974759414781056 99
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 2997565 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 2997565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---