Simulation Results: sysrst_ctrl

 
11/03/2026 18:08:48 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.44 %
  • code
  • 92.56 %
  • assert
  • 93.87 %
  • func
  • 63.88 %
  • line
  • 97.23 %
  • branch
  • 97.40 %
  • cond
  • 94.46 %
  • toggle
  • 100.00 %
  • FSM
  • 73.72 %
Validation stages
V1
100.00%
V2
95.65%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.400s 0.000us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 6.190s 0.000us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.530s 0.000us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 3.990s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.580s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.100s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 136.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.910s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.960s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.100s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.910s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 49.830s 0.000us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 80.460s 0.000us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.340s 0.000us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 5.080s 0.000us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.010s 0.000us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 5.000s 0.000us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.400s 0.000us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.460s 0.000us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 4.830s 0.000us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 42.850s 0.000us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 5.320s 0.000us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.730s 0.000us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.610s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 1.660s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 1.660s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.580s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 2.100s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.910s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.410s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.580s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 2.100s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.910s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.410s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 22.240s 0.000us 1 1 100.00
sysrst_ctrl_sec_cm 22.100s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 22.240s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 10.250s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
sysrst_ctrl_ultra_low_pwr 5050621235623355322838633630891254089941937628657879276829113815142693005511 651
UVM_ERROR @ 3887564182 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 3887585016 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3887585016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---