Simulation Results: flash_ctrl

 
12/03/2026 17:23:11 DVSim: v1.14.2 sha: bbf86e0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.81 %
  • code
  • 94.51 %
  • assert
  • 96.76 %
  • func
  • 96.16 %
  • line
  • 95.94 %
  • branch
  • 97.10 %
  • cond
  • 94.23 %
  • toggle
  • 97.53 %
  • FSM
  • 87.76 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.73%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 49.350s 0.000us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.240s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 12.330s 0.000us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.540s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 30.010s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 22.600s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.840s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.540s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 22.600s 0.000us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.400s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.330s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.340s 0.000us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 33.460s 0.000us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1131.120s 0.000us 1 1 100.00
flash_ctrl_hw_rma_reset 628.270s 0.000us 1 1 100.00
flash_ctrl_lcmgr_intg 6.490s 0.000us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1572.990s 0.000us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 159.020s 0.000us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 9.850s 0.000us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1641.030s 0.000us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 44.620s 0.000us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.690s 0.000us 1 1 100.00
flash_ctrl_rw_evict_all_en 19.290s 0.000us 1 1 100.00
flash_ctrl_re_evict 18.100s 0.000us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 30.300s 0.000us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 30.300s 0.000us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 145.580s 0.000us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 13.380s 0.000us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 475.850s 0.000us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 486.860s 0.000us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 321.350s 0.000us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 819.160s 0.000us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.350s 0.000us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 114.760s 0.000us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.430s 0.000us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.450s 0.000us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 382.020s 0.000us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 70.170s 0.000us 1 1 100.00
flash_ctrl_otp_reset 49.510s 0.000us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1131.120s 0.000us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 87.020s 0.000us 1 1 100.00
flash_ctrl_intr_wr 61.960s 0.000us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 132.650s 0.000us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 158.720s 0.000us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 35.980s 0.000us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 33.260s 0.000us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.740s 0.000us 1 1 100.00
flash_ctrl_ro_derr 94.540s 0.000us 1 1 100.00
flash_ctrl_rw_derr 167.020s 0.000us 1 1 100.00
flash_ctrl_derr_detect 97.790s 0.000us 1 1 100.00
flash_ctrl_integrity 413.890s 0.000us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.020s 0.000us 1 1 100.00
flash_ctrl_ro_serr 92.440s 0.000us 1 1 100.00
flash_ctrl_rw_serr 101.930s 0.000us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 53.380s 0.000us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 36.000s 0.000us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 125.210s 0.000us 1 1 100.00
flash_ctrl_write_word_sweep 6.590s 0.000us 1 1 100.00
flash_ctrl_read_word_sweep 8.030s 0.000us 1 1 100.00
flash_ctrl_ro 77.840s 0.000us 1 1 100.00
flash_ctrl_rw 419.990s 0.000us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 24.680s 0.000us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 896.080s 0.000us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 187.050s 0.000us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.960s 0.000us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.030s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.820s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.820s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.330s 0.000us 1 1 100.00
flash_ctrl_csr_rw 7.540s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 22.600s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.450s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.330s 0.000us 1 1 100.00
flash_ctrl_csr_rw 7.540s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 22.600s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.450s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 46.680s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 46.680s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 46.680s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 46.680s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 42.390s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 177.010s 0.000us 1 1 100.00
flash_ctrl_sec_cm 1471.800s 0.000us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 177.010s 0.000us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 177.010s 0.000us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.110s 0.000us 1 1 100.00
flash_ctrl_wr_intg 6.560s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 49.350s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 49.510s 0.000us 1 1 100.00
flash_ctrl_disable 10.430s 0.000us 1 1 100.00
flash_ctrl_sec_info_access 31.590s 0.000us 1 1 100.00
flash_ctrl_connect 6.450s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.030s 0.000us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.540s 0.000us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 46.680s 0.000us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.540s 0.000us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 46.680s 0.000us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.540s 0.000us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 46.680s 0.000us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.430s 0.000us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.110s 0.000us 1 1 100.00
flash_ctrl_access_after_disable 5.730s 0.000us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 12.890s 0.000us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.430s 0.000us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 13.380s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 419.990s 0.000us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 101.930s 0.000us 1 1 100.00
flash_ctrl_rw_derr 167.020s 0.000us 1 1 100.00
flash_ctrl_integrity 413.890s 0.000us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1131.120s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1471.800s 0.000us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1471.800s 0.000us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1471.800s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1471.800s 0.000us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.340s 0.000us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.850s 0.000us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 0 1 0.00
flash_ctrl_phy_ack_consistency 5.390s 0.000us 0 1 0.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1471.800s 0.000us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1471.800s 0.000us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1471.800s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.070s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 326.210s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
flash_ctrl_phy_ack_consistency 69449609056806872455255551034738502403660968363073940823332561190726652817879 116
UVM_ERROR @ 5121.3 ns: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x3b)
UVM_INFO @ 5121.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---