Simulation Results

Simulation Results: otp_ctrl

12/03/2026 17:23:11 DVSim: v1.14.2 sha: bbf86e0 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
80.68 %

code
76.74 %

assert
93.99 %

func
71.31 %

line
88.52 %

branch
83.03 %

cond
90.02 %

toggle
81.14 %

FSM
40.97 %

Validation stages

V1		100.00%
V2		84.00%
V2S		92.86%
V3		50.00%

11/11 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	1.590s	0.000us	1	1	100.00
smoke				1	1	100.00
	otp_ctrl_smoke	4.590s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	1.450s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	otp_ctrl_csr_rw	1.550s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	3.650s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	5.460s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	otp_ctrl_csr_mem_rw_with_rand_reset	2.330s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	otp_ctrl_csr_rw	1.550s	0.000us	1	1	100.00
	otp_ctrl_csr_aliasing	5.460s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	1.330s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.320s	0.000us	1	1	100.00

21/25 passed

84.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				1	1	100.00
	otp_ctrl_partition_walk	15.710s	0.000us	1	1	100.00
init_fail				1	1	100.00
	otp_ctrl_init_fail	2.800s	0.000us	1	1	100.00
partition_check				0	2	0.00
	otp_ctrl_background_chks	37.780s	0.000us	0	1	0.00
	otp_ctrl_check_fail	2.990s	0.000us	0	1	0.00
regwen_during_otp_init				1	1	100.00
	otp_ctrl_regwen	4.290s	0.000us	1	1	100.00
partition_lock				1	1	100.00
	otp_ctrl_dai_lock	10.990s	0.000us	1	1	100.00
interface_key_check				1	1	100.00
	otp_ctrl_parallel_key_req	19.410s	0.000us	1	1	100.00
lc_interactions				2	2	100.00
	otp_ctrl_parallel_lc_req	30.100s	0.000us	1	1	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
otp_dai_errors				0	1	0.00
	otp_ctrl_dai_errs	2.710s	0.000us	0	1	0.00
otp_macro_errors				0	1	0.00
	otp_ctrl_macro_errs	9.790s	0.000us	0	1	0.00
test_access				1	1	100.00
	otp_ctrl_test_access	37.510s	0.000us	1	1	100.00
stress_all				1	1	100.00
	otp_ctrl_stress_all	72.660s	0.000us	1	1	100.00
intr_test				1	1	100.00
	otp_ctrl_intr_test	1.360s	0.000us	1	1	100.00
alert_test				1	1	100.00
	otp_ctrl_alert_test	2.630s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	otp_ctrl_tl_errors	3.190s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	otp_ctrl_tl_errors	3.190s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	otp_ctrl_csr_hw_reset	1.450s	0.000us	1	1	100.00
	otp_ctrl_csr_rw	1.550s	0.000us	1	1	100.00
	otp_ctrl_csr_aliasing	5.460s	0.000us	1	1	100.00
	otp_ctrl_same_csr_outstanding	1.680s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	otp_ctrl_csr_hw_reset	1.450s	0.000us	1	1	100.00
	otp_ctrl_csr_rw	1.550s	0.000us	1	1	100.00
	otp_ctrl_csr_aliasing	5.460s	0.000us	1	1	100.00
	otp_ctrl_same_csr_outstanding	1.680s	0.000us	1	1	100.00

V2S

52/56 passed

92.86 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
tl_intg_err				2	2	100.00
	otp_ctrl_tl_intg_err	7.300s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
prim_count_check				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
prim_fsm_check				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	otp_ctrl_tl_intg_err	7.300s	0.000us	1	1	100.00
sec_cm_secret_mem_scramble				1	1	100.00
	otp_ctrl_smoke	4.590s	0.000us	1	1	100.00
sec_cm_part_mem_digest				1	1	100.00
	otp_ctrl_smoke	4.590s	0.000us	1	1	100.00
sec_cm_dai_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_kdi_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_lci_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_part_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_scrmbl_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_timer_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_dai_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_kdi_seed_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_kdi_entropy_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_lci_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_part_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_scrmbl_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_timer_integ_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_timer_cnsty_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_timer_lfsr_redun				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_dai_fsm_local_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_lci_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
sec_cm_kdi_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
sec_cm_part_fsm_local_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
	otp_ctrl_macro_errs	9.790s	0.000us	0	1	0.00
sec_cm_scrmbl_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
sec_cm_timer_fsm_local_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_dai_fsm_global_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_lci_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
sec_cm_kdi_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
sec_cm_part_fsm_global_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
	otp_ctrl_macro_errs	9.790s	0.000us	0	1	0.00
sec_cm_scrmbl_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
sec_cm_timer_fsm_global_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	3.100s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_part_data_reg_integrity				1	1	100.00
	otp_ctrl_init_fail	2.800s	0.000us	1	1	100.00
sec_cm_part_data_reg_bkgn_chk				0	1	0.00
	otp_ctrl_check_fail	2.990s	0.000us	0	1	0.00
sec_cm_part_mem_regren				1	1	100.00
	otp_ctrl_dai_lock	10.990s	0.000us	1	1	100.00
sec_cm_part_mem_sw_unreadable				1	1	100.00
	otp_ctrl_dai_lock	10.990s	0.000us	1	1	100.00
sec_cm_part_mem_sw_unwritable				1	1	100.00
	otp_ctrl_dai_lock	10.990s	0.000us	1	1	100.00
sec_cm_lc_part_mem_sw_noaccess				1	1	100.00
	otp_ctrl_dai_lock	10.990s	0.000us	1	1	100.00
sec_cm_access_ctrl_mubi				1	1	100.00
	otp_ctrl_dai_lock	10.990s	0.000us	1	1	100.00
sec_cm_token_valid_ctrl_mubi				1	1	100.00
	otp_ctrl_smoke	4.590s	0.000us	1	1	100.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	otp_ctrl_dai_lock	10.990s	0.000us	1	1	100.00
sec_cm_test_bus_lc_gated				1	1	100.00
	otp_ctrl_smoke	4.590s	0.000us	1	1	100.00
sec_cm_test_tl_lc_gate_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	152.920s	0.000us	1	1	100.00
sec_cm_direct_access_config_regwen				1	1	100.00
	otp_ctrl_regwen	4.290s	0.000us	1	1	100.00
sec_cm_check_trigger_config_regwen				1	1	100.00
	otp_ctrl_smoke	4.590s	0.000us	1	1	100.00
sec_cm_check_config_regwen				1	1	100.00
	otp_ctrl_smoke	4.590s	0.000us	1	1	100.00
sec_cm_macro_mem_integrity				0	1	0.00
	otp_ctrl_macro_errs	9.790s	0.000us	0	1	0.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				1	1	100.00
	otp_ctrl_low_freq_read	10.660s	0.000us	1	1	100.00
stress_all_with_rand_reset				0	1	0.00
	otp_ctrl_stress_all_with_rand_reset	1.460s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_check_error does not trigger!
	otp_ctrl_background_chks	51406037805648845216147002768874027320210324728556392296915975502165699746009	16509	UVM_ERROR @ 16606773512 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger! UVM_INFO @ 16606773512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_
	otp_ctrl_dai_errs	22033291659493691668818224425604846975547667808299306027658304287942039563600	2647	UVM_ERROR @ 84309341 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2720113058 [0xa221a1a2] vs 3139811234 [0xbb25b7a2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0 UVM_INFO @ 84309341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.intr_state
	otp_ctrl_check_fail	23807463411572804498976807487655602064354846972684307298970438076472421434321	2537	UVM_ERROR @ 1130395288 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state UVM_INFO @ 1130395288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:*
	otp_ctrl_macro_errs	788729275681119344824636298105929470313910834531958444967495733772871461972	4699	UVM_ERROR @ 2175824866 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20 UVM_INFO @ 2175824866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =
	otp_ctrl_stress_all_with_rand_reset	74410753065748453818047716470208853755569257039964932401959305794953389907999	93	UVM_ERROR @ 27675005 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1 UVM_INFO @ 27675005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---