Simulation Results

Simulation Results: spi_device/1r1w

12/03/2026 17:23:11 DVSim: v1.14.2 sha: bbf86e0 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.90 %

code
93.28 %

assert
94.64 %

func
72.77 %

line
99.07 %

branch
98.30 %

cond
96.14 %

toggle
83.54 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		96.15%
V2S		100.00%
unmapped		100.00%

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	55.020s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	0.930s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.940s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	17.640s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	10.370s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	1.770s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.940s	0.000us	1	1	100.00
	spi_device_csr_aliasing	10.370s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.720s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.300s	0.000us	1	1	100.00

50/52 passed

96.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.810s	0.000us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.800s	0.000us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.720s	0.000us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	0.800s	0.000us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	0.800s	0.000us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	7.030s	0.000us	1	1	100.00
	spi_device_tpm_sts_read	0.850s	0.000us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	23.910s	0.000us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	10.980s	0.000us	1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	3.460s	0.000us	1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	3.460s	0.000us	1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	3.400s	0.000us	1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	3.400s	0.000us	1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	3.400s	0.000us	1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	3.400s	0.000us	1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	3.400s	0.000us	1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	4.500s	0.000us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	7.120s	0.000us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	7.120s	0.000us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	7.120s	0.000us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	1.740s	0.000us	1	1	100.00
	spi_device_read_buffer_direct	10.900s	0.000us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	7.120s	0.000us	1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	147.470s	0.000us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	1.950s	0.000us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	1.950s	0.000us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	55.020s	0.000us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	18.170s	0.000us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	31.870s	0.000us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.840s	0.000us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.750s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	2.880s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	2.880s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	0.930s	0.000us	1	1	100.00
	spi_device_csr_rw	1.940s	0.000us	1	1	100.00
	spi_device_csr_aliasing	10.370s	0.000us	1	1	100.00
	spi_device_same_csr_outstanding	2.190s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	0.930s	0.000us	1	1	100.00
	spi_device_csr_rw	1.940s	0.000us	1	1	100.00
	spi_device_csr_aliasing	10.370s	0.000us	1	1	100.00
	spi_device_same_csr_outstanding	2.190s	0.000us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	9.240s	0.000us	1	1	100.00
	spi_device_sec_cm	1.940s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	9.240s	0.000us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	192.900s	0.000us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	77222572816364354674425096366199228111979752160807225154131524660684646259857	76	UVM_ERROR @ 967350 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[101]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 967350 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 967350 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[997]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	68565914157937489830848203897070478406174988058996070928403703111533843286032	76	UVM_ERROR @ 917483 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb58b21 [101101011000101100100001] vs 0x0 [0]) UVM_ERROR @ 994483 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8f61de [100011110110000111011110] vs 0x0 [0]) UVM_ERROR @ 1056483 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x451b29 [10001010001101100101001] vs 0x0 [0]) UVM_ERROR @ 1093483 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x50aa5 [1010000101010100101] vs 0x0 [0]) UVM_ERROR @ 1126483 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x402917 [10000000010100100010111] vs 0x0 [0])