Simulation Results: sysrst_ctrl

 
12/03/2026 17:23:11 DVSim: v1.14.2 sha: bbf86e0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.20 %
  • code
  • 92.61 %
  • assert
  • 89.94 %
  • func
  • 55.04 %
  • line
  • 97.12 %
  • branch
  • 97.29 %
  • cond
  • 94.92 %
  • toggle
  • 100.00 %
  • FSM
  • 73.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.060s 0.000us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.540s 0.000us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.980s 0.000us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.790s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.820s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.190s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 40.680s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.150s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.190s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 78.180s 0.000us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 10.160s 0.000us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 4.110s 0.000us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 5.600s 0.000us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.960s 0.000us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.880s 0.000us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.860s 0.000us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.790s 0.000us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.960s 0.000us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 11.030s 0.000us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 7.880s 0.000us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.510s 0.000us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.510s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.250s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.250s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.820s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 4.190s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.150s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.820s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 4.190s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.150s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 7.180s 0.000us 1 1 100.00
sysrst_ctrl_sec_cm 46.930s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 7.180s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 11.670s 0.000us 1 1 100.00