Simulation Results: adc_ctrl

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.30 %
  • code
  • 96.97 %
  • assert
  • 95.62 %
  • func
  • 18.31 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 93.42 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 11.350s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.270s 0.000us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.640s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 13.040s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.450s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.260s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.640s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 2.450s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 280.820s 0.000us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 416.580s 0.000us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 87.280s 0.000us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 188.090s 0.000us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 283.480s 0.000us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 168.890s 0.000us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 455.550s 0.000us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.570s 0.000us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.350s 0.000us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 9.610s 0.000us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 93.990s 0.000us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 36.360s 0.000us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.120s 0.000us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.600s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.990s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.990s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.270s 0.000us 1 1 100.00
adc_ctrl_csr_rw 1.640s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 2.450s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.840s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.270s 0.000us 1 1 100.00
adc_ctrl_csr_rw 1.640s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 2.450s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.840s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.110s 0.000us 1 1 100.00
adc_ctrl_tl_intg_err 5.200s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 5.200s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 4.930s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 23594915894718589222504053499739454587726980876973830701526676873003279926701 317
UVM_ERROR @ 1547540905 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1547540905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 30443935979827095180433530114910150959513681814597196722994708120373958793503 337
UVM_ERROR @ 17263212563 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 17263212563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---