Simulation Results: chip

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.77 %
  • code
  • 85.03 %
  • assert
  • 97.37 %
  • func
  • 47.90 %
  • line
  • 94.34 %
  • branch
  • 93.65 %
  • cond
  • 88.74 %
  • toggle
  • 91.27 %
  • FSM
  • 57.14 %
Validation stages
V1
95.65%
V2
84.56%
V2S
100.00%
V3
60.00%
unmapped
62.50%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 121.950s 0.000us 1 1 100.00
chip_sw_example_rom 63.620s 0.000us 1 1 100.00
chip_sw_example_manufacturer 152.750s 0.000us 1 1 100.00
chip_sw_example_concurrency 158.860s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 149.170s 0.000us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 225.080s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 776.530s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4556.580s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 43.920s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4556.580s 0.000us 1 1 100.00
chip_csr_rw 225.080s 0.000us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.710s 0.000us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 327.690s 0.000us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 327.690s 0.000us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 327.690s 0.000us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 350.090s 0.000us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 350.090s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx1 333.540s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx2 404.150s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx3 348.510s 0.000us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 402.160s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1022.230s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 698.250s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 156.280s 0.000us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 156.280s 0.000us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 170.730s 0.000us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 165.500s 0.000us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 135.980s 0.000us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 145.010s 0.000us 1 1 100.00
chip_tap_straps_testunlock0 198.450s 0.000us 1 1 100.00
chip_tap_straps_rma 363.650s 0.000us 1 1 100.00
chip_tap_straps_prod 506.010s 0.000us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 174.160s 0.000us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 813.150s 0.000us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 332.700s 0.000us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 332.700s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 605.450s 0.000us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1519.690s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 373.650s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 569.090s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3556.890s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 152.760s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 652.850s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.010s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1645.560s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 177.100s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 411.340s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 122.530s 0.000us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 209.730s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 323.300s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 235.360s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 177.590s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 235.360s 0.000us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 162.830s 0.000us 1 1 100.00
chip_sw_aes_smoketest 129.970s 0.000us 1 1 100.00
chip_sw_aon_timer_smoketest 142.050s 0.000us 1 1 100.00
chip_sw_clkmgr_smoketest 174.610s 0.000us 1 1 100.00
chip_sw_csrng_smoketest 115.730s 0.000us 1 1 100.00
chip_sw_entropy_src_smoketest 728.430s 0.000us 1 1 100.00
chip_sw_gpio_smoketest 207.270s 0.000us 1 1 100.00
chip_sw_hmac_smoketest 216.720s 0.000us 1 1 100.00
chip_sw_kmac_smoketest 235.240s 0.000us 1 1 100.00
chip_sw_otbn_smoketest 1046.980s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 282.770s 0.000us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 199.610s 0.000us 1 1 100.00
chip_sw_rv_plic_smoketest 165.460s 0.000us 1 1 100.00
chip_sw_rv_timer_smoketest 149.970s 0.000us 1 1 100.00
chip_sw_rstmgr_smoketest 137.560s 0.000us 1 1 100.00
chip_sw_sram_ctrl_smoketest 144.040s 0.000us 1 1 100.00
chip_sw_uart_smoketest 189.640s 0.000us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 161.660s 0.000us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 318.710s 0.000us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7416.260s 0.000us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2578.620s 0.000us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 130.050s 0.000us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 245.890s 0.000us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 151.590s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6779.530s 0.000us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7159.960s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 62.280s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 62.280s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4556.580s 0.000us 1 1 100.00
chip_same_csr_outstanding 2796.790s 0.000us 1 1 100.00
chip_csr_hw_reset 149.170s 0.000us 1 1 100.00
chip_csr_rw 225.080s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4556.580s 0.000us 1 1 100.00
chip_same_csr_outstanding 2796.790s 0.000us 1 1 100.00
chip_csr_hw_reset 149.170s 0.000us 1 1 100.00
chip_csr_rw 225.080s 0.000us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 12.070s 0.000us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.220s 0.000us 1 1 100.00
xbar_smoke_large_delays 38.140s 0.000us 1 1 100.00
xbar_smoke_slow_rsp 40.300s 0.000us 1 1 100.00
xbar_random_zero_delays 19.170s 0.000us 1 1 100.00
xbar_random_large_delays 301.770s 0.000us 1 1 100.00
xbar_random_slow_rsp 155.480s 0.000us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 33.880s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 4.520s 0.000us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 16.980s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 4.520s 0.000us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 66.210s 0.000us 1 1 100.00
xbar_access_same_device_slow_rsp 247.770s 0.000us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 24.790s 0.000us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 105.040s 0.000us 1 1 100.00
xbar_stress_all_with_error 197.690s 0.000us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 185.370s 0.000us 1 1 100.00
xbar_stress_all_with_reset_error 60.680s 0.000us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2578.620s 0.000us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2142.300s 0.000us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2526.900s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 1969.560s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2543.130s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2578.960s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2527.840s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2583.550s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 16.640s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 20.970s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 19.230s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 21.700s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 16.650s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 17.240s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 16.600s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 16.360s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 16.380s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.110s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 15.970s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.580s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.990s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.880s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.150s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.420s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 17.200s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 16.640s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.690s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.420s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 15.870s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.060s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17.630s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.760s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 16.510s 0.000us 0 1 0.00
rom_e2e_asm_init 4 5 80.00
rom_e2e_asm_init_test_unlocked0 1987.480s 0.000us 1 1 100.00
rom_e2e_asm_init_dev 2455.810s 0.000us 1 1 100.00
rom_e2e_asm_init_prod 2439.040s 0.000us 1 1 100.00
rom_e2e_asm_init_prod_end 2462.420s 0.000us 1 1 100.00
rom_e2e_asm_init_rma 262.680s 0.000us 0 1 0.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 2388.790s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 4303.680s 0.000us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2284.610s 0.000us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2514.140s 0.000us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3096.000s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3096.000s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 129.640s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 152.760s 0.000us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 193.980s 0.000us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 163.760s 0.000us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1040.670s 0.000us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 171.330s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 300.090s 0.000us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 412.270s 0.000us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 557.960s 0.000us 1 1 100.00
chip_plic_all_irqs_10 255.160s 0.000us 1 1 100.00
chip_plic_all_irqs_20 362.140s 0.000us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 226.630s 0.000us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1063.170s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 158.590s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 152.630s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 779.440s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1001.770s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 729.440s 0.000us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8008.190s 0.000us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 292.910s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 282.770s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 292.910s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 637.670s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 637.670s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 316.490s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 417.290s 0.000us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 618.410s 0.000us 1 1 100.00
chip_sw_aes_idle 163.760s 0.000us 1 1 100.00
chip_sw_hmac_enc_idle 199.610s 0.000us 1 1 100.00
chip_sw_kmac_idle 132.860s 0.000us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 276.240s 0.000us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 296.230s 0.000us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 298.730s 0.000us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 240.760s 0.000us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 882.180s 0.000us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 365.420s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 354.500s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 376.170s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 360.020s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 397.260s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 391.700s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 605.450s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 555.400s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 376.170s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 360.020s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 373.650s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 569.090s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3556.890s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 152.760s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 652.850s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.010s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1645.560s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 177.100s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 411.340s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 122.530s 0.000us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 102.900s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 365.060s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 680.560s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3033.980s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 168.260s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 166.930s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 933.570s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 188.860s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 376.410s 0.000us 1 1 100.00
chip_sw_flash_init_reduced_freq 1300.350s 0.000us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3941.920s 0.000us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 605.450s 0.000us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 373.800s 0.000us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 233.830s 0.000us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 412.270s 0.000us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 779.440s 0.000us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 839.420s 0.000us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 163.310s 0.000us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 478.360s 0.000us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 206.040s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 4745.220s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 147.340s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 702.540s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 147.340s 0.000us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 839.420s 0.000us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 176.450s 0.000us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1413.890s 0.000us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 552.580s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 569.090s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 375.840s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 373.650s 0.000us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3396.870s 0.000us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1413.890s 0.000us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 253.680s 0.000us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1216.140s 0.000us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 239.830s 0.000us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3396.870s 0.000us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 239.830s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 239.830s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 239.830s 0.000us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 239.830s 0.000us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 412.270s 0.000us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 158.140s 0.000us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 496.170s 0.000us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 458.360s 0.000us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 458.360s 0.000us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 194.970s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.010s 0.000us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 199.610s 0.000us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 904.760s 0.000us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 749.700s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 388.720s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 390.250s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 421.280s 0.000us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 306.120s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1216.140s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1645.560s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1410.620s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1040.670s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 1990.310s 0.000us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 177.450s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac 177.060s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 177.100s 0.000us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1216.140s 0.000us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 689.010s 0.000us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 157.020s 0.000us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 850.920s 0.000us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 132.860s 0.000us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 300.090s 0.000us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 145.010s 0.000us 1 1 100.00
chip_tap_straps_rma 363.650s 0.000us 1 1 100.00
chip_tap_straps_prod 506.010s 0.000us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 182.300s 0.000us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 689.010s 0.000us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 689.010s 0.000us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 689.010s 0.000us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 673.160s 0.000us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_prim_tl_access 158.140s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 208.770s 0.000us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 239.830s 0.000us 0 1 0.00
chip_sw_flash_rma_unlocked 3396.870s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 246.310s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 404.770s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 602.240s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 549.010s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 689.010s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1216.140s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 279.580s 0.000us 1 1 100.00
chip_sw_sram_ctrl_execution_main 628.900s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 555.400s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 365.420s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 354.500s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 376.170s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 360.020s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 397.260s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 391.700s 0.000us 1 1 100.00
chip_tap_straps_dev 145.010s 0.000us 1 1 100.00
chip_tap_straps_rma 363.650s 0.000us 1 1 100.00
chip_tap_straps_prod 506.010s 0.000us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 195.190s 0.000us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 83.100s 0.000us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 72.780s 0.000us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 100.010s 0.000us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 208.770s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1401.430s 0.000us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 542.780s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 708.650s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 660.320s 0.000us 1 1 100.00
chip_sw_lc_walkthrough_rma 326.380s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1401.430s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 67.820s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 53.630s 0.000us 1 1 100.00
rom_volatile_raw_unlock 59.790s 0.000us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3457.630s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3556.890s 0.000us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 618.410s 0.000us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 618.410s 0.000us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 618.410s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 305.780s 0.000us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 689.010s 0.000us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1413.890s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 305.780s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1216.140s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 323.370s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 167.160s 0.000us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1413.890s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 305.780s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1216.140s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 323.370s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 167.160s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 689.010s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 359.570s 0.000us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 182.300s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 158.140s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 246.310s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 404.770s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 602.240s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 549.010s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 689.010s 0.000us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 158.140s 0.000us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 869.660s 0.000us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 414.470s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 993.100s 0.000us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 244.330s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 369.670s 0.000us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 458.600s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1126.110s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 399.510s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 637.670s 0.000us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 949.750s 0.000us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 334.740s 0.000us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 414.470s 0.000us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 297.290s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 248.340s 0.000us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 325.580s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 288.440s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1575.640s 0.000us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 641.010s 0.000us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1016.360s 0.000us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1900.360s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 150.590s 0.000us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 412.270s 0.000us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 279.580s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 279.580s 0.000us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 1016.360s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1575.640s 0.000us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 334.740s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 282.770s 0.000us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 301.560s 0.000us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 310.060s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 283.780s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1063.170s 0.000us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 142.150s 0.000us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 412.270s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1001.770s 0.000us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 477.700s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 493.000s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 187.110s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 167.160s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 310.060s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 310.060s 0.000us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 788.400s 0.000us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 941.830s 0.000us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 301.560s 0.000us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 172.070s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 271.110s 0.000us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 363.650s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 208.770s 0.000us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 557.960s 0.000us 1 1 100.00
chip_plic_all_irqs_10 255.160s 0.000us 1 1 100.00
chip_plic_all_irqs_20 362.140s 0.000us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 153.960s 0.000us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 155.450s 0.000us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2578.620s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 537.790s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 227.590s 0.000us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 195.600s 0.000us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 195.520s 0.000us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 323.370s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 411.340s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 395.400s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 342.420s 0.000us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 628.900s 0.000us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 412.270s 0.000us 1 1 100.00
chip_sw_data_integrity_escalation 332.700s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 641.010s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1336.020s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 178.020s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 237.830s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 398.090s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1336.020s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1336.020s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2512.440s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2512.440s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 366.200s 0.000us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3096.000s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 159.120s 0.000us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 199.000s 0.000us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 279.780s 0.000us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 337.430s 0.000us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1110.630s 0.000us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5137.800s 0.000us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1881.250s 0.000us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 133.240s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 202.840s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 117.010s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 8948.460s 0.000us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 974.540s 0.000us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 184.060s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 162.640s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 195.290s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 67.210s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 73.570s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 65.920s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 7.838s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 219.560s 0.000us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 289.470s 0.000us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1134.970s 0.000us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1376.650s 0.000us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 247.770s 0.000us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 552.030s 0.000us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 94.980s 0.000us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 181.860s 0.000us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 253.700s 0.000us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 361.820s 0.000us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1016.360s 0.000us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 184.060s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 162.640s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 195.290s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 344.760s 0.000us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 412.270s 0.000us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5138.520s 0.000us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5138.520s 0.000us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 192.870s 0.000us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 350.090s 0.000us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2995.410s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 5 8 62.50
chip_sival_flash_info_access 206.850s 0.000us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 362.650s 0.000us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 6.390s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 166.600s 0.000us 1 1 100.00
chip_sw_otp_ctrl_descrambling 173.020s 0.000us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 259.690s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 12.339s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 191.960s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 47296835294538068327005757893031571457651216953387861302416486640318134054432 217
UVM_ERROR @ 2581.651904 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@33569) { a_addr: 'h1036c a_data: 'h2edbe0dc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h27 a_opcode: 'h4 a_user: 'h1a293 d_param: 'h0 d_source: 'h27 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2581.651904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 50016818964698085651072546892668784555507011111308719921149189524109528817156 224
UVM_ERROR @ 2498.323724 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31657) { a_addr: 'h106fc a_data: 'ha24edc2b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h1a2ac d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2498.323724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 83721106325236667221993464347953995487423387881029122426188461995857509649823 338
UVM_ERROR @ 3854.116320 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@129137) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 3854.116320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 71103230409126190289370896962863231378893758340521672954904059008765893831421 247
UVM_ERROR @ 8140.934556 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10460 read out mismatch
UVM_INFO @ 8140.934556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 16306120371898047755300806037403066940323638539674540818992008974062281612530 320
UVM_ERROR @ 3667.625199 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3667.625199 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 60205750856751539446526812633027420428730667490056547824731886864371684541233 309
UVM_ERROR @ 3301.101426 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 3301.101426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 75023832718812833283456853118405919194422245195829455087051384083587456484257 342
UVM_ERROR @ 7455.191624 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7455.191624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 77304818599208854804124651990222750866662997998589677968996316049254374273259 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3016.148908 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3016.148908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 50019566729123813298699297290515616361059970718617736481360274801358050775995 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2996.023992 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2996.023992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 14742019292265465155995969358106724047674380928519510278438623955667543461651 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 42458868580365712356820143751530197675335980030468463268914792907913924954272 369
UVM_ERROR @ 7705.009547 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 7705.009547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 109703935990447046500874714352055899546871398900033154542581689769686343790758 369
UVM_ERROR @ 11616.880560 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 11616.880560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 24278782713912398764601997118781918477648828491717882077645095149273123802840 346
UVM_ERROR @ 5935.931251 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 5935.931251 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 40175254425817677568639635973544604234137504749987832618676087179050320415196 327
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 10316.868000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10316.868000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 6749382503564558381236605824010636525436127411476881038164207990257935400915 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7619.018500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7619.018500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 54997889922000753822464461951749428589138983601856805316603057492562333191415 316
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 5995.709000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5995.709000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 61991983619709962945603192521600837620859587555305690509438487414575271328618 332
UVM_ERROR @ 34647.104038 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34647.104038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!
chip_sw_alert_test 110232167487156616353332785236622179093651698724049380171219521767658059431774 307
UVM_ERROR @ 3120.604400 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 51!
UVM_INFO @ 3120.604400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 32275810958023476463372735905957025177451193462272189886048401452731071553923 308
UVM_ERROR @ 2548.265744 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2548.265744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 49381210053223674706281930505408482096249163185125841669522328990909101608258 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 84739634066316023355103388180249818141621908878564345330304499146142321205750 343
UVM_ERROR @ 3891.983921 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3891.983921 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 66930967442670802894125105877450177805201616212276676452907363183491182805127 317
UVM_ERROR @ 4375.780637 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 4375.780637 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 77712198363440950942239502642228223210851211797380071035291178010962004329406 None
Another command (pid=1933507) is running. Waiting for it to complete on the server (server_pid=935787)...
Another command (pid=1935003) is running. Waiting for it to complete on the server (server_pid=935787)...
Another command (pid=1934460) is running. Waiting for it to complete on the server (server_pid=935787)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 80336116431568185123119509069347615584964983141125128156068601758563395057173 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 48658946984646176324088574785141760921592908543672866812291277458729771356747 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 86894343708313809649365254081132156509142081598150200620360715512060052795610 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 36180637409693636806544219537118254738256214853078456510268210234249128353651 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 84242801890381019593040053562990502932168849698454289910950505609763617136460 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 10173979222399350398873394957720361861324710797238007365039741317972965049755 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 57508811712923487365233163982316193130986487851988278595065442480371173993459 312
UVM_ERROR @ 3868.193000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3868.193000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 53147070181092646217543072466160540896789430012146751681623627343421564784937 318
UVM_ERROR @ 3050.312500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3050.312500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 15313886191206778189348211643623765062740438794424480953963185038513819738930 327
UVM_ERROR @ 13990.577450 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 13990.577450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 79667008874087408995828613607401876938839431522079024939895395204828901976198 351
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 109948672014655423306394440317906084634559505034486769898684776278061280937469 351
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 62593846659357957254091761552475148665796860909255652716471402901794009235955 351
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 106262748025773629074840596050567899437355147080685544301090783051566518683095 351
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 106973471814747436484810142541316206811387278612177511385234710596313425805599 351
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 83175975633707864428701270771065002712767772551046878639970967236047106717230 349
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 15626079365118019878647330210030564464167590969782865131201428761214179060757 349
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 10986632346730453073433629125881598091890997605159529792599325455759134783799 349
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 101816606799930809575999022875169462100899317282461227221256732798301293354931 349
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 68801414872688169384357082212161777976721395680268827760533957652155071528833 346
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 58363605222057233717526759835475920497930704635150604610550688057933647025722 360
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 49696762140132159861213760948244977878811805228643077615630956793020067212051 358
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 94212844176939652873068416867081713811464121086339714934059578339440613321519 360
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 4914314507080736212980756657744825960176765479866797048174110666256481872028 323
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 87843251247970882019175644342918241094256913236852478133618855993231765966412 325
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 5259663902595950935957147458064698047971175183922374336765166534024757977076 323
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 102785004309352128756609441356027094534397768826932633011056603959237685014061 361
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 92256853969451978742456611078372468479138507540025958780255823653035834145260 325
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 73882731632588649948945446117691862133108596844724139912564554806745044703516 360
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 97006906139825290172141759342055166086365573538096114241500112491220428454370 324
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 36768178463936819724723338400188347008828068659983898391992375329963423359078 322
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 107785556898026299360145212159796127900722104059481125299423828997057723023395 323
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 106804689416471231432927956540665729763528564183660392496104386665793162074886 323
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 109613505125974976674544999911330826869385803424733458042662887905246957452834 324
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 33152287698166930060871651506272538045602623634094694339239460928205189909139 323
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
rom_e2e_asm_init_rma 78414365392934691949704556965025603006772088485057372082853330236421911603938 306
UVM_FATAL @ 10010.180001 us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
UVM_INFO @ 10010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_test_unlocked0 112351735727410313735882372774372462489039601565543233328066487951600681688582 318
UVM_ERROR @ 4566.855960 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
UVM_INFO @ 4566.855960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_dev 40170406156681501992646152264652273308677047818166356290128889319204760715280 318
UVM_ERROR @ 4520.658046 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
UVM_INFO @ 4520.658046 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 73348873395006891272098089314600064721803851802195979558804495553007784391420 319
UVM_ERROR @ 16963.185045 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16963.185045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 107689317004483557939828730445156387707498003070434565577875621658469946770649 319
UVM_ERROR @ 15553.070768 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 15553.070768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 49747269138704511283464308345556287123665101699427011719425531968666370031959 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 4400.459608 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4400.459608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---