Simulation Results: clkmgr

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.34 %
  • code
  • 98.46 %
  • assert
  • 95.62 %
  • func
  • 85.93 %
  • line
  • 99.19 %
  • branch
  • 98.96 %
  • cond
  • 94.15 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.800s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.690s 0.000us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.720s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.740s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.890s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.900s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.720s 0.000us 1 1 100.00
clkmgr_csr_aliasing 0.890s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.810s 0.000us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.810s 0.000us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.650s 0.000us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.690s 0.000us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.800s 0.000us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 2.950s 0.000us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.530s 0.000us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 2.950s 0.000us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 0.780s 0.000us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.670s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.880s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.880s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.690s 0.000us 1 1 100.00
clkmgr_csr_rw 0.720s 0.000us 1 1 100.00
clkmgr_csr_aliasing 0.890s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 0.980s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.690s 0.000us 1 1 100.00
clkmgr_csr_rw 0.720s 0.000us 1 1 100.00
clkmgr_csr_aliasing 0.890s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 0.980s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_tl_intg_err 2.020s 0.000us 1 1 100.00
clkmgr_sec_cm 4.400s 0.000us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.260s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.260s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.260s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.260s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.480s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.020s 0.000us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 2.950s 0.000us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.530s 0.000us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.260s 0.000us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.760s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.080s 0.000us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.630s 0.000us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.720s 0.000us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.710s 0.000us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.720s 0.000us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.400s 0.000us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.720s 0.000us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.720s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.400s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.440s 0.000us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 37.600s 0.000us 1 1 100.00