Simulation Results: edn/edn1

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.80 %
  • code
  • 83.23 %
  • assert
  • 97.14 %
  • func
  • 80.04 %
  • line
  • 97.88 %
  • branch
  • 92.42 %
  • cond
  • 89.38 %
  • toggle
  • 95.57 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.990s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.750s 0.000us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.690s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.990s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.020s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.180s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.690s 0.000us 1 1 100.00
edn_csr_aliasing 1.020s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.580s 0.000us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.580s 0.000us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.580s 0.000us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.730s 0.000us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 0.000us 1 1 100.00
errs 1 1 100.00
edn_err 0.900s 0.000us 1 1 100.00
disable 2 2 100.00
edn_disable 0.810s 0.000us 1 1 100.00
edn_disable_auto_req_mode 0.830s 0.000us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.870s 0.000us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 0.000us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.700s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.240s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.240s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.750s 0.000us 1 1 100.00
edn_csr_rw 0.690s 0.000us 1 1 100.00
edn_csr_aliasing 1.020s 0.000us 1 1 100.00
edn_same_csr_outstanding 0.970s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.750s 0.000us 1 1 100.00
edn_csr_rw 0.690s 0.000us 1 1 100.00
edn_csr_aliasing 1.020s 0.000us 1 1 100.00
edn_same_csr_outstanding 0.970s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.690s 0.000us 1 1 100.00
edn_tl_intg_err 1.610s 0.000us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 0.000us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 0.000us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.690s 0.000us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.690s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.690s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.690s 0.000us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 0.000us 1 1 100.00
edn_sec_cm 2.690s 0.000us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 0.000us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.610s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 36.840s 0.000us 1 1 100.00