Simulation Results: flash_ctrl

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.63 %
  • code
  • 94.27 %
  • assert
  • 96.76 %
  • func
  • 95.85 %
  • line
  • 95.95 %
  • branch
  • 97.12 %
  • cond
  • 93.51 %
  • toggle
  • 97.69 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
98.46%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 71.500s 0.000us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 8.720s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 12.670s 0.000us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.560s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 30.030s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 41.200s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.990s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.560s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 41.200s 0.000us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.620s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.510s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.690s 0.000us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 25.760s 0.000us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1379.200s 0.000us 1 1 100.00
flash_ctrl_hw_rma_reset 731.840s 0.000us 1 1 100.00
flash_ctrl_lcmgr_intg 5.840s 0.000us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1649.180s 0.000us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 165.630s 0.000us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 121.820s 0.000us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2972.640s 0.000us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 47.720s 0.000us 1 1 100.00
rd_buff_eviction_w_ecc 2 3 66.67
flash_ctrl_rw_evict 18.330s 0.000us 1 1 100.00
flash_ctrl_rw_evict_all_en 12.610s 0.000us 0 1 0.00
flash_ctrl_re_evict 19.270s 0.000us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 44.390s 0.000us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 44.390s 0.000us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 157.420s 0.000us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.510s 0.000us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 274.610s 0.000us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 391.790s 0.000us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 284.160s 0.000us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 774.190s 0.000us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.790s 0.000us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 109.940s 0.000us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 12.570s 0.000us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.700s 0.000us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 358.400s 0.000us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 108.210s 0.000us 1 1 100.00
flash_ctrl_otp_reset 51.760s 0.000us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1379.200s 0.000us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 127.930s 0.000us 1 1 100.00
flash_ctrl_intr_wr 49.780s 0.000us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 163.220s 0.000us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 143.690s 0.000us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 45.740s 0.000us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.810s 0.000us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.950s 0.000us 1 1 100.00
flash_ctrl_ro_derr 91.080s 0.000us 1 1 100.00
flash_ctrl_rw_derr 131.300s 0.000us 1 1 100.00
flash_ctrl_derr_detect 106.380s 0.000us 1 1 100.00
flash_ctrl_integrity 510.750s 0.000us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.220s 0.000us 1 1 100.00
flash_ctrl_ro_serr 95.470s 0.000us 1 1 100.00
flash_ctrl_rw_serr 133.220s 0.000us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 27.960s 0.000us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 44.230s 0.000us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 139.460s 0.000us 1 1 100.00
flash_ctrl_write_word_sweep 8.210s 0.000us 1 1 100.00
flash_ctrl_read_word_sweep 6.220s 0.000us 1 1 100.00
flash_ctrl_ro 73.630s 0.000us 1 1 100.00
flash_ctrl_rw 411.910s 0.000us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.580s 0.000us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 627.340s 0.000us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 41.440s 0.000us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.930s 0.000us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.570s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.990s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.990s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.670s 0.000us 1 1 100.00
flash_ctrl_csr_rw 7.560s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 41.200s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.730s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.670s 0.000us 1 1 100.00
flash_ctrl_csr_rw 7.560s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 41.200s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.730s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 33.550s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 33.550s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 33.550s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 33.550s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 21.360s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 137.770s 0.000us 1 1 100.00
flash_ctrl_sec_cm 1589.300s 0.000us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 137.770s 0.000us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 137.770s 0.000us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.860s 0.000us 1 1 100.00
flash_ctrl_wr_intg 6.240s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 71.500s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 51.760s 0.000us 1 1 100.00
flash_ctrl_disable 12.570s 0.000us 1 1 100.00
flash_ctrl_sec_info_access 35.820s 0.000us 1 1 100.00
flash_ctrl_connect 6.700s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.500s 0.000us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.560s 0.000us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 33.550s 0.000us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.560s 0.000us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 33.550s 0.000us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.560s 0.000us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 33.550s 0.000us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 12.570s 0.000us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.860s 0.000us 1 1 100.00
flash_ctrl_access_after_disable 5.770s 0.000us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 12.740s 0.000us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 12.570s 0.000us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.510s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 411.910s 0.000us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 133.220s 0.000us 1 1 100.00
flash_ctrl_rw_derr 131.300s 0.000us 1 1 100.00
flash_ctrl_integrity 510.750s 0.000us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1379.200s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1589.300s 0.000us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1589.300s 0.000us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1589.300s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1589.300s 0.000us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.260s 0.000us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.650s 0.000us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.330s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1589.300s 0.000us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1589.300s 0.000us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1589.300s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 17.260s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 254.910s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: *
flash_ctrl_rw_evict_all_en 73640228117510465016940731269488280483519702902964666203983107997342246761104 108
UVM_ERROR @ 19023.1 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 19023.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---