Simulation Results: i2c

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.47 %
  • code
  • 81.03 %
  • assert
  • 95.98 %
  • func
  • 79.39 %
  • line
  • 96.35 %
  • branch
  • 92.12 %
  • cond
  • 84.59 %
  • toggle
  • 89.24 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
87.76%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 16.750s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 8.820s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.870s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.690s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.190s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.170s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.110s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.690s 0.000us 1 1 100.00
i2c_csr_aliasing 1.170s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 2.350s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 46.940s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 3249.890s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.710s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 148.790s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 121.840s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.980s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 5.950s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 3.970s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 67.100s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 7.390s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.440s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 3.590s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 22.690s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.830s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 21.260s 0.000us 1 1 100.00
i2c_target_intr_smoke 5.650s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.560s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.150s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 505.460s 0.000us 1 1 100.00
i2c_target_stress_rd 21.260s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 6.620s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.630s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 14.050s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.880s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 21.830s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.790s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.070s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 3249.890s 0.000us 1 1 100.00
i2c_host_perf_precise 5.890s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 7.390s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.160s 0.000us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.910s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.950s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.790s 0.000us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 2.100s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.530s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.700s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.850s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.310s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.310s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.870s 0.000us 1 1 100.00
i2c_csr_rw 0.690s 0.000us 1 1 100.00
i2c_csr_aliasing 1.170s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.940s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.870s 0.000us 1 1 100.00
i2c_csr_rw 0.690s 0.000us 1 1 100.00
i2c_csr_aliasing 1.170s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.940s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.770s 0.000us 1 1 100.00
i2c_sec_cm 0.850s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.770s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 10.700s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.940s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 20.940s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 38414928908390276249190303840502656682243864125833885772303045882655738754704 102
UVM_ERROR @ 264107720 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 264107720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 52577630359751429987783297579622102849823852182635736208931638042282108403127 182
UVM_ERROR @ 17399655719 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 17399655719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 21202134967125889530340973826999577685345249545576712870655836937854994991364 84
UVM_ERROR @ 1983307241 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1983307241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
i2c_target_unexp_stop 40693475377597624793882159565428989678153367592169278771781369620419202011655 79
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 300833691 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 300833691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 71249129942625756513239814193837215633844862411512947899464833338524309064212 79
UVM_FATAL @ 10004385686 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10004385686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 106808172191055509574836847009695171507052907239305677041996746004474875872480 104
UVM_ERROR @ 3079854880 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3079854880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 93936451741454611283841144178010557409043911445452779180045372493370519450882 91
UVM_ERROR @ 836208354 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 836208354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_mode_toggle 15919500869111579903404029606894896015903461592631466488390503529053910667965 90
UVM_ERROR @ 211957816 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @25401
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 68666065809372981806659316866530431651357666288977819828209099310165656421095 78
UVM_ERROR @ 838132957 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 838132957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---