Simulation Results: kmac/unmasked

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.59 %
  • code
  • 87.82 %
  • assert
  • 97.75 %
  • func
  • 92.21 %
  • line
  • 97.16 %
  • branch
  • 94.78 %
  • cond
  • 91.04 %
  • toggle
  • 99.92 %
  • FSM
  • 56.20 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 46.650s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.980s 0.000us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.160s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 5.640s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.520s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.100s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.160s 0.000us 1 1 100.00
kmac_csr_aliasing 5.520s 0.000us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.810s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.290s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 40.080s 0.000us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 342.060s 0.000us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 24.790s 0.000us 1 1 100.00
kmac_test_vectors_sha3_256 1573.950s 0.000us 1 1 100.00
kmac_test_vectors_sha3_384 18.850s 0.000us 1 1 100.00
kmac_test_vectors_sha3_512 14.830s 0.000us 1 1 100.00
kmac_test_vectors_shake_128 2215.970s 0.000us 1 1 100.00
kmac_test_vectors_shake_256 226.920s 0.000us 1 1 100.00
kmac_test_vectors_kmac 1.640s 0.000us 1 1 100.00
kmac_test_vectors_kmac_xof 2.550s 0.000us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 103.720s 0.000us 1 1 100.00
app 1 1 100.00
kmac_app 213.110s 0.000us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 228.050s 0.000us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 13.450s 0.000us 1 1 100.00
error 1 1 100.00
kmac_error 119.120s 0.000us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 6.290s 0.000us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 25.000s 0.000us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 7.840s 0.000us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 13.800s 0.000us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 28.800s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.450s 0.000us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 687.480s 0.000us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.780s 0.000us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.080s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.220s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.220s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.980s 0.000us 1 1 100.00
kmac_csr_rw 1.160s 0.000us 1 1 100.00
kmac_csr_aliasing 5.520s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.900s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.980s 0.000us 1 1 100.00
kmac_csr_rw 1.160s 0.000us 1 1 100.00
kmac_csr_aliasing 5.520s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.900s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.610s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.610s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.610s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.610s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.120s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 19.240s 0.000us 1 1 100.00
kmac_tl_intg_err 2.890s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.890s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.450s 0.000us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 46.650s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 103.720s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.610s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 19.240s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 19.240s 0.000us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 19.240s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 46.650s 0.000us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.450s 0.000us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 19.240s 0.000us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 148.880s 0.000us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 46.650s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 28.610s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26)
kmac_sideload_invalid 42138003903449774408069856825513109480014003856737366598426484285111698744133 106
UVM_FATAL @ 10734416855 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf094c000, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 10734416855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 24767504471963901415349840958784959906828881716190288687817101540688533851331 97
UVM_ERROR @ 3096399476 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3096399476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---