Simulation Results: lc_ctrl/volatile_unlock_enabled

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.64 %
  • code
  • 84.02 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.06 %
  • branch
  • 93.47 %
  • cond
  • 79.07 %
  • toggle
  • 87.90 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
97.50%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.470s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.890s 0.000us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.090s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.120s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.680s 0.000us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.670s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.910s 0.000us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_ctrl_prog_failure 1.670s 0.000us 1 1 100.00
lc_ctrl_errors 4.910s 0.000us 1 1 100.00
lc_ctrl_security_escalation 7.430s 0.000us 1 1 100.00
lc_ctrl_jtag_state_failure 33.040s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.450s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 15.970s 0.000us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.680s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.710s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.450s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 15.970s 0.000us 1 1 100.00
lc_ctrl_jtag_access 2.110s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.030s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.950s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.220s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.940s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.610s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.160s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.180s 0.000us 1 1 100.00
lc_ctrl_jtag_alert_test 0.770s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.440s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.040s 0.000us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 228.840s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.840s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.890s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.890s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.080s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.080s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.720s 0.000us 1 1 100.00
lc_ctrl_tl_intg_err 1.390s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.390s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.720s 0.000us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.720s 0.000us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.720s 0.000us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.720s 0.000us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.720s 0.000us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.720s 0.000us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.720s 0.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.420s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.720s 0.000us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.430s 0.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.680s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.710s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.030s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.030s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.190s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.720s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.720s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 59.820s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 65636491424549226441230855792450573463909718708764768952739270278349850636093 8333
UVM_ERROR @ 11261470083 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 11261470083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---