Simulation Results: pwrmgr

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.68 %
  • code
  • 94.57 %
  • assert
  • 96.08 %
  • func
  • 96.38 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.48 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.690s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.650s 0.000us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.610s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.420s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.730s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.750s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.610s 0.000us 1 1 100.00
pwrmgr_csr_aliasing 0.730s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.940s 0.000us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.940s 0.000us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.610s 0.000us 1 1 100.00
pwrmgr_lowpower_invalid 0.680s 0.000us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.780s 0.000us 1 1 100.00
pwrmgr_reset_invalid 0.780s 0.000us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.780s 0.000us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.150s 0.000us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.830s 0.000us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.740s 0.000us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.020s 0.000us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.540s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.670s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.670s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 0.000us 1 1 100.00
pwrmgr_csr_rw 0.610s 0.000us 1 1 100.00
pwrmgr_csr_aliasing 0.730s 0.000us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 0.000us 1 1 100.00
pwrmgr_csr_rw 0.610s 0.000us 1 1 100.00
pwrmgr_csr_aliasing 0.730s 0.000us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.760s 0.000us 0 1 0.00
pwrmgr_sec_cm 0.710s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.710s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.710s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.760s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.440s 0.000us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.150s 0.000us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.750s 0.000us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.580s 0.000us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.710s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.710s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.710s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.590s 0.000us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.530s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.670s 0.000us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.610s 0.000us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.610s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.640s 0.000us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 5.160s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 47660136700120374589057264251950970616913855545390767418251789245030493762533 82
UVM_ERROR @ 12108155 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 12108155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 95799327273674290784054433269961987044049775901349158774451765044614878031234 86
UVM_ERROR @ 29459374 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 29459374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
pwrmgr_escalation_timeout 48229677407822802210158981064560753669525172001255662897392342781322681837986 75
UVM_ERROR @ 1213820338 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 1213820338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---