Simulation Results: rom_ctrl/32kb

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.75 %
  • code
  • 93.31 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 95.39 %
  • toggle
  • 99.44 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
58.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.460s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.550s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.090s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.420s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.290s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.120s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.090s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 4.290s 0.000us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.620s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.080s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.540s 0.000us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.330s 0.000us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.230s 0.000us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.730s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.230s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.230s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.550s 0.000us 1 1 100.00
rom_ctrl_csr_rw 4.090s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 4.290s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.110s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.550s 0.000us 1 1 100.00
rom_ctrl_csr_rw 4.090s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 4.290s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.110s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.770s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 188.950s 0.000us 1 1 100.00
rom_ctrl_tl_intg_err 43.800s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 188.950s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 188.950s 0.000us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 188.950s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 188.950s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.460s 0.000us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.460s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.460s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 43.800s 0.000us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 7.230s 0.000us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 13.300s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.770s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 188.950s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 181.590s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 97584376694569611551863345773993780732820736539925694680082656406017367114162 88
UVM_ERROR @ 368313837 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 368313837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---