Simulation Results: sysrst_ctrl

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.76 %
  • code
  • 93.67 %
  • assert
  • 94.92 %
  • func
  • 68.69 %
  • line
  • 97.82 %
  • branch
  • 97.81 %
  • cond
  • 95.79 %
  • toggle
  • 100.00 %
  • FSM
  • 76.92 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.280s 0.000us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.790s 0.000us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.980s 0.000us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.660s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 8.360s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.340s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 29.140s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.630s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.720s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.340s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.630s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 202.700s 0.000us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 116.520s 0.000us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 4.060s 0.000us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 5.300s 0.000us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.750s 0.000us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.850s 0.000us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.310s 0.000us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 0.900s 0.000us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 5.320s 0.000us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 21.320s 0.000us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 16.770s 0.000us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.520s 0.000us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.180s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.440s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.440s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.360s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 4.340s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.630s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.230s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.360s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 4.340s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.630s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.230s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 70.790s 0.000us 1 1 100.00
sysrst_ctrl_tl_intg_err 17.980s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 17.980s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.050s 0.000us 1 1 100.00