Simulation Results: uart

 
16/03/2026 17:30:52 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.43 %
  • code
  • 96.74 %
  • assert
  • 97.12 %
  • func
  • 53.42 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.78 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.500s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 0.000us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.640s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.930s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.700s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.720s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.640s 0.000us 1 1 100.00
uart_csr_aliasing 0.700s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 35.780s 0.000us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.500s 0.000us 1 1 100.00
uart_tx_rx 35.780s 0.000us 1 1 100.00
parity_error 2 2 100.00
uart_intr 9.280s 0.000us 1 1 100.00
uart_rx_parity_err 65.670s 0.000us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 35.780s 0.000us 1 1 100.00
uart_intr 9.280s 0.000us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 103.740s 0.000us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 332.780s 0.000us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 20.340s 0.000us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 9.280s 0.000us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 9.280s 0.000us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 9.280s 0.000us 1 1 100.00
perf 1 1 100.00
uart_perf 548.820s 0.000us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.010s 0.000us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.010s 0.000us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.510s 0.000us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.700s 0.000us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.630s 0.000us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 19.340s 0.000us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 93.800s 0.000us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 234.080s 0.000us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.670s 0.000us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.450s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.450s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 0.000us 1 1 100.00
uart_csr_rw 0.640s 0.000us 1 1 100.00
uart_csr_aliasing 0.700s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.670s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 0.000us 1 1 100.00
uart_csr_rw 0.640s 0.000us 1 1 100.00
uart_csr_aliasing 0.700s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.670s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.830s 0.000us 1 1 100.00
uart_tl_intg_err 1.320s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.320s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 27.210s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark
uart_noise_filter 61701894687987563172320642604892909278143117216701601992782926057445719634410 74
UVM_ERROR @ 168321570 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 168321570 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
UVM_ERROR @ 329214829 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 329214829 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 329214829 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark