Simulation Results: adc_ctrl

 
17/03/2026 17:25:29 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.42 %
  • code
  • 96.87 %
  • assert
  • 95.95 %
  • func
  • 18.44 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 92.93 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.370s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.940s 0.000us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.390s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 24.490s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.410s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.080s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.390s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 3.410s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 45.610s 0.000us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 67.750s 0.000us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 255.260s 0.000us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 266.930s 0.000us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 366.850s 0.000us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 263.610s 0.000us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 521.690s 0.000us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 153.440s 0.000us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 7.020s 0.000us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 71.710s 0.000us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 161.230s 0.000us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 727.230s 0.000us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.040s 0.000us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.730s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.310s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.310s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.940s 0.000us 1 1 100.00
adc_ctrl_csr_rw 1.390s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 3.410s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.210s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.940s 0.000us 1 1 100.00
adc_ctrl_csr_rw 1.390s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 3.410s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.210s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 13.760s 0.000us 1 1 100.00
adc_ctrl_tl_intg_err 15.330s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 15.330s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 9.190s 0.000us 1 1 100.00