Simulation Results: alert_handler

 
17/03/2026 17:25:29 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.30 %
  • code
  • 93.43 %
  • assert
  • 98.33 %
  • func
  • 82.15 %
  • line
  • 99.73 %
  • branch
  • 99.80 %
  • cond
  • 93.78 %
  • toggle
  • 94.80 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 40.030s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.420s 0.000us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.960s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 335.030s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 46.240s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.960s 0.000us 1 1 100.00
alert_handler_csr_aliasing 46.240s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 45.080s 0.000us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 47.480s 0.000us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1998.100s 0.000us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 10.280s 0.000us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 40.030s 0.000us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 13.320s 0.000us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 31.560s 0.000us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 162.180s 0.000us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 851.350s 0.000us 1 1 100.00
alert_handler_lpg_stub_clk 1268.730s 0.000us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1258.990s 0.000us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 44.770s 0.000us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.230s 0.000us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.760s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.610s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.610s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.420s 0.000us 1 1 100.00
alert_handler_csr_rw 5.960s 0.000us 1 1 100.00
alert_handler_csr_aliasing 46.240s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 16.220s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.420s 0.000us 1 1 100.00
alert_handler_csr_rw 5.960s 0.000us 1 1 100.00
alert_handler_csr_aliasing 46.240s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 16.220s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 56.950s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 56.950s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 56.950s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 56.950s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 394.710s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_tl_intg_err 55.670s 0.000us 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 55.670s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 56.950s 0.000us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 40.030s 0.000us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 40.030s 0.000us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 40.030s 0.000us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 40.030s 0.000us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 10.280s 0.000us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 851.350s 0.000us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 10.280s 0.000us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1998.100s 0.000us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1998.100s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.200s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 352.000s 0.000us 1 1 100.00